SSRAM with AHB bus interface source code

AHB_SRRAM
.........\work
.........\....\_info
.........\....\_temp
.........\....\@s@r@a@m_8@x4@x4096
.........\....\...................\_primary.vhd
.........\....\...................\_primary.dat
.........\....\...................\verilog.asm
.........\....\@a@h@b_@testsys
.........\....\...............\_primary.vhd
.........\....\...............\_primary.dat
.........\....\...............\verilog.asm
.........\....\@r@a1@s@h
.........\....\.........\_primary.vhd
.........\....\.........\_primary.dat
.........\....\.........\verilog.asm
.........\....\@a@h@b_@h@c_master
.........\....\..................\_primary.vhd
.........\....\..................\_primary.dat
.........\....\..................\verilog.asm
.........\....\_opt
.........\....\....\work__info
.........\....\....\_deps
.........\....\....\work_@a@h@b@decoder_fast.dt2
.........\....\....\work_@a@h@b@mux@s2@m_fast.dt2
.........\....\....\work_@a@h@b2@a@p@b_fast.dt2
.........\....\....\work_@a@p@b@regs_fast.dt2
.........\....\....\work_@a@p@b@intcon_fast.dt2
.........\....\....\work_@a@h@b@a@p@b@sys_fast.dt2
.........\....\....\work_@a@h@b@z@b@t@r@a@m_fast.dt2
.........\....\....\work_@a@h@b@a@h@b@top_fast.asm
.........\....\....\work_@a@h@b@a@h@b@top_fast.dt2
.........\....\_opt1
.........\....\.....\work__info
.........\....\.....\work_@a@h@b_@h@c_master_fast.asm
.........\....\.....\work_@a@h@b_@h@c_master_fast.dt2
.........\....\.....\_deps
.........\....\@a@p@b@regs
.........\....\...........\_primary.vhd
.........\....\...........\_primary.dat
.........\....\...........\verilog.asm
.........\....\@a@h@b@a@p@b@sys
.........\....\................\_primary.vhd
.........\....\................\_primary.dat
.........\....\................\verilog.asm
.........\....\@a@p@b@intcon
.........\....\.............\_primary.vhd
.........\....\.............\_primary.dat
.........\....\.............\verilog.asm
.........\....\@m@y@i@p
.........\....\........\_primary.vhd
.........\....\........\_primary.dat
.........\....\@a@h@b@mux@s2@m
.........\....\...............\_primary.vhd
.........\....\...............\_primary.dat
.........\....\...............\verilog.asm
.........\....\@a@h@b2@a@p@b
.........\....\.............\_primary.vhd
.........\....\.............\_primary.dat
.........\....\.............\verilog.asm
.........\....\@a@h@b@decoder
.........\....\..............\_primary.vhd
.........\....\..............\_primary.dat
.........\....\..............\verilog.asm
.........\....\@a@h@b@z@b@t@r@a@m
.........\....\..................\_primary.vhd
.........\....\..................\_primary.dat
.........\....\..................\verilog.asm
.........\....\@a@h@b@a@h@b@top
.........\....\................\_primary.vhd
.........\....\................\_primary.dat
.........\....\................\verilog.asm
.........\....\_opt2
.........\....\.....\work__info
.........\....\.....\work_@a@h@b@decoder_fast.dt2
.........\....\.....\work_@a@h@b@mux@s2@m_fast.dt2
.........\....\.....\work_@a@h@b2@a@p@b_fast.dt2
.........\....\.....\work_@a@p@b@regs_fast.dt2
.........\....\.....\work_@a@p@b@intcon_fast.dt2
.........\....\.....\work_@a@h@b@a@p@b@sys_fast.dt2
.........\....\.....\work_@a@h@b@z@b@t@r@a@m_fast.dt2
.........\....\.....\work_@a@h@b@a@h@b@top_fast.dt2
.........\....\.....\work_@r@a1@s@h_fast.dt2
.........\....\.....\work_@s@r@a@m_8@x4@x4096_fast.dt2
.........\....\.....\work_@a@h@b_@h@c_master_fast.dt2
.........\....\.....\_deps
.........\....\.....\work_@a@h@b_@testsys_fast.asm
.........\....\.....\work_@a@h@b_@testsys_fast.dt2
.........\vsim.wlf
.........\AHBAHBTop.v
.........\AHBAPBSys.v
.........\AHBDecoder.v
.........\AHB2APB.v
.........\AHBMuxS2M.v
.........\AHBZBTRAM.v
.........\APBIntcon.v
.........\APBRegs.v
.........\MyIP.v
.........\AHB_Testbench.v.bak
.........\AHB_SRAM.cr.mti

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