设计控制器，源代码！Verilog代码！

ddrct_gen_xm_4_001\default.css
..................\Readme.htm
..................\tutorial
..................\xm
..................\..\ver4
..................\..\....\eval
..................\..\....\....\readme.txt
..................\..\....\....\simulation
..................\..\....\....\..........\scripts
..................\..\....\....\..........\.......\eval_ddr_sim_verilog.do
..................\..\....\....\..........\.......\eval_ddr_sim_vhdl.do
..................\..\....\....\testbench
..................\..\....\....\.........\verilog
..................\..\....\....\.........\.......\test_ddr_sdram_mem_sim.v
..................\..\....\....\.........\vhdl
..................\..\....\....\.........\....\test_ddr_sdram_mem_sim.vhd
..................\..\....\....\tests
..................\..\....\....\.....\stim_ddr_test_01.v
..................\..\....\gui_script
..................\..\....\..........\module_gen.zip
..................\..\....\lib
..................\..\....\...\modelsim
..................\..\....\...\........\IP_work
..................\..\....\...\........\.......\cal
..................\..\....\...\........\.......\...\verilog.psm
..................\..\....\...\........\.......\...\_primary.dat
..................\..\....\...\........\.......\...\_primary.vhd
..................\..\....\...\........\.......\cal_cesm
..................\..\....\...\........\.......\........\verilog.psm
..................\..\....\...\........\.......\........\_primary.dat
..................\..\....\...\........\.......\........\_primary.vhd
..................\..\....\...\........\.......\cal_csm
..................\..\....\...\........\.......\.......\verilog.psm
..................\..\....\...\........\.......\.......\_primary.dat
..................\..\....\...\........\.......\.......\_primary.vhd
..................\..\....\...\........\.......\cal_ctsm
..................\..\....\...\........\.......\........\verilog.psm
..................\..\....\...\........\.......\........\_primary.dat
..................\..\....\...\........\.......\........\_primary.vhd
..................\..\....\...\........\.......\cdl
..................\..\....\...\........\.......\...\verilog.psm
..................\..\....\...\........\.......\...\_primary.dat
..................\..\....\...\........\.......\...\_primary.vhd
..................\..\....\...\........\.......\ddrct_gen_xm_4_001
..................\..\....\...\........\.......\..................\verilog.psm
..................\..\....\...\........\.......\..................\_primary.dat
..................\..\....\...\........\.......\..................\_primary.vhd
..................\..\....\...\........\.......\init_sm
..................\..\....\...\........\.......\.......\verilog.psm
..................\..\....\...\........\.......\.......\_primary.dat
..................\..\....\...\........\.......\.......\_primary.vhd
..................\..\....\...\........\.......\row_addr_tab
..................\..\....\...\........\.......\............\verilog.psm
..................\..\....\...\........\.......\............\_primary.dat
..................\..\....\...\........\.......\............\_primary.vhd
..................\..\....\...\........\.......\_info
..................\..\....\par
..................\..\....\...\ddrct_gen_xm_4_001.lpc
..................\..\....\...\ddrct_gen_xm_4_001.ngo
..................\..\....\...\ddrct_gen_xm_4_001_synplify.prf
..................\..\....\...\post_route_trace_synplify.prf
..................\..\....\source
..................\..\....\......\ddr_sdram_mem_top_synp.sdc
..................\..\....\......\verilog
..................\..\....\......\.......\albuf.v
..................\..\....\......\.......\bidi_cell.v
..................\..\....\......\.......\cal_dvgen.v
..................\..\....\......\.......\ddrct_gen_xm_4_001.v
..................\..\....\......\.......\ddrct_gen_xm_4_001_params.v
..................\..\....\......\.......\ddr_data_io.v
..................\..\....\......\.......\ddr_dm_io.v
..................\..\....\......\.......\ddr_dqs_io.v
...

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