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S6_LCD_VHDL

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 409kb
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lcd
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S6_LCD_VHDL\S6_LCD_VHDL\Doc\程序说明.txt
...........\...........\Proj\cmp_state.ini
...........\...........\....\db\cntr_ea7.tdf
...........\...........\....\..\cntr_ed8.tdf
...........\...........\....\..\cntr_hd8.tdf
...........\...........\....\..\mux_ooc.tdf
...........\...........\....\..\prev_cmp_LCD_Test.qmsg
...........\...........\....\..\prev_cmp_Proj.asm.qmsg
...........\...........\....\..\prev_cmp_Proj.fit.qmsg
...........\...........\....\..\prev_cmp_Proj.map.qmsg
...........\...........\....\..\prev_cmp_Proj.sim.qmsg
...........\...........\....\..\prev_cmp_Proj.tan.qmsg
...........\...........\....\..\Proj.asm.qmsg
...........\...........\....\..\Proj.cbx.xml
...........\...........\....\..\Proj.cmp.rdb
...........\...........\....\..\Proj.cmp2.ddb
...........\...........\....\..\Proj.dbp
...........\...........\....\..\Proj.db_info
...........\...........\....\..\Proj.eco.cdb
...........\...........\....\..\Proj.eds_overflow
...........\...........\....\..\Proj.fit.qmsg
...........\...........\....\..\Proj.fnsim.cdb
...........\...........\....\..\Proj.fnsim.hdb
...........\...........\....\..\Proj.fnsim.qmsg
...........\...........\....\..\Proj.hier_info
...........\...........\....\..\Proj.hif
...........\...........\....\..\Proj.map.cdb
...........\...........\....\..\Proj.map.hdb
...........\...........\....\..\Proj.map.logdb
...........\...........\....\..\Proj.map.qmsg
...........\...........\....\..\Proj.pre_map.cdb
...........\...........\....\..\Proj.pre_map.hdb
...........\...........\....\..\Proj.psp
...........\...........\....\..\Proj.pss
...........\...........\....\..\Proj.rpp.qmsg
...........\...........\....\..\Proj.rtlv.hdb
...........\...........\....\..\Proj.rtlv_sg.cdb
...........\...........\....\..\Proj.rtlv_sg_swap.cdb
...........\...........\....\..\Proj.sgate.rvd
...........\...........\....\..\Proj.sgate_sm.rvd
...........\...........\....\..\Proj.sgdiff.cdb
...........\...........\....\..\Proj.sgdiff.hdb
...........\...........\....\..\Proj.sim.cvwf
...........\...........\....\..\Proj.sim.hdb
...........\...........\....\..\Proj.sim.qmsg
...........\...........\....\..\Proj.sim.rdb
...........\...........\....\..\Proj.simfam
...........\...........\....\..\Proj.sld_design_entry.sci
...........\...........\....\..\Proj.sld_design_entry_dsc.sci
...........\...........\....\..\Proj.syn_hier_info
...........\...........\....\..\Proj.tan.qmsg
...........\...........\....\..\Proj.tis_db_list.ddb
...........\...........\....\..\Proj_cmp.qrpt
...........\...........\....\..\wed.wsf
...........\...........\....\div16.bsf
...........\...........\....\lcd.bsf
...........\...........\....\LCD_test.bdf
...........\...........\....\lcd_test.bsf
...........\...........\....\LCD_Test.qpf
...........\...........\....\LCD_Test.qws
...........\...........\....\Proj.asm.rpt
...........\...........\....\Proj.cdf
...........\...........\....\Proj.done
...........\...........\....\Proj.dpf
...........\...........\....\Proj.fit.eqn
...........\...........\....\Proj.fit.rpt
...........\...........\....\Proj.fit.smsg
...........\...........\....\Proj.fit.summary
...........\...........\....\Proj.flow.rpt
...........\...........\....\Proj.map.eqn
...........\...........\....\Proj.map.rpt
...........\...........\....\Proj.map.summary
...........\...........\....\Proj.pin
...........\...........\....\Proj.pof
...........\...........\....\Proj.qsf
...........\...........\....\Proj.sim.rpt
...........\...........\....\Proj.sof
...........\...........\....\Proj.tan.rpt
...........\...........\....\Proj.tan.summary
...........\...........\....\Proj.vwf
...........\...........\....\Proj_assignment_defaults.qdf
...........\...........\....\Proj_description.txt
...........\...........\Src\char_ram.vhd
...........\...........\...\DIV16.v
...........\...........\...\lcd.vhd
...........\...........\Proj\db
...........\...........\Doc
...........\...........\Proj
...........\...........\Src
...........\S6_LCD_VHDL
S6_LCD_VHDL
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