We are using parameters is the test bench and passing them to the state machine using parameter passing We are using tasks to control the flow of the testbench We are using hierarchical naming to access the state variable in the state machine from the test bench. Finally we are using test bench messages which allow us to monitor the current state from the simulation waveform viewer (assuming we change the bus radix of the message to ascii.

statemechine\statemechne.v
statemechine

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