VerilogHDL的135个经典设计实例.rar

source
......\chap9
......\.....\bidir.v
......\.....\bidir2.v
......\.....\code_83.v
......\.....\decode47.v
......\.....\decoder_38.v
......\.....\dff.v
......\.....\dff1.v
......\.....\dff2.v
......\.....\encoder8_3.v
......\.....\gate1.v
......\.....\gate2.v
......\.....\gate3.v
......\.....\jk_ff.v
......\.....\johnson.v
......\.....\latch_1.v
......\.....\latch_2.v
......\.....\latch_8.v
......\.....\mac.v
......\.....\mac_tp.v
......\.....\map_lpm_ram.v
......\.....\mpc.v
......\.....\mpc_tp.v
......\.....\mux_case.v
......\.....\mux_if.v
......\.....\parity.v
......\.....\ram256x8.v
......\.....\reg8.v
......\.....\rom.v
......\.....\serial_pal.v
......\.....\shifter.v
......\.....\tri_1.v
......\.....\tri_2.v
......\.....\updown_count.v
......\chap8
......\.....\add8_tp.v
......\.....\carry_udp.v
......\.....\carry_udpx1.v
......\.....\carry_udpx2.v
......\.....\count8_tp.v
......\.....\delay.v
......\.....\dff.v
......\.....\dff_udp.v
......\.....\latch.v
......\.....\mult_tp.v
......\.....\mux31.v
......\.....\mux_tp.v
......\.....\random_tp.v
......\.....\rom.v
......\.....\test1.v
......\.....\test2.v
......\.....\time_dif.v
......\chap7
......\.....\add4_1.v
......\.....\add4_2.v
......\.....\add4_3.v
......\.....\count4.v
......\.....\full_add1.v
......\.....\full_add2.v
......\.....\full_add3.v
......\.....\full_add4.v
......\.....\full_add5.v
......\.....\half_add1.v
......\.....\half_add2.v
......\.....\half_add3.v
......\.....\half_add4.v
......\.....\mux2_1a.v
......\.....\mux2_1b.v
......\.....\mux2_1c.v
......\.....\mux4_1a.v
......\.....\mux4_1b.v
......\.....\mux4_1c.v
......\.....\mux4_1d.v
......\chap6
......\.....\alutask.v
......\.....\alu_tp.v
......\.....\code_83.v
......\.....\count.v
......\.....\funct.v
......\.....\funct_tp.v
......\.....\paral1.v
......\.....\paral2.v
......\.....\serial1.v
......\.....\serial2.v
......\chap5
......\.....\adder.v
......\.....\adder16.v
......\.....\alu.v
......\.....\block.v
......\.....\buried_ff.v
......\.....\compile.v
......\.....\count.v
......\.....\count60.v
......\.....\decode4_7.v
......\.....\loop1.v
......\.....\loop2.v
......\.....\loop3.v
......\.....\mult_for.v
......\.....\mult_repeat.v

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