Using vhdl design a mips small cpu, with no running water, there are r class, i type, j class instruction have ~*

mipsfinal\alu.tbw
.........\ALU.vhd
.........\alu.xwv
.........\alu.xwv_bak
.........\alucontrol_vhdl.prj
.........\ALUCTRL.vhd
.........\alutest.jhd
.........\alutest.tbw
.........\alutest.xwv
.........\alutest.xwv_bak
.........\alu_vhdl.prj
.........\controltest.tbw
.........\controltest.xwv
.........\controltest.xwv_bak
.........\controltst_bencher.prj
.........\Control_Unit.vhd
.........\control_unit_vhdl.prj
.........\DATA_mem.vhd
.........\data_mem_vhdl.prj
.........\instrmemtest.tbw
.........\instrmemtest.xwv
.........\instrmemtest.xwv_bak
.........\Instr_mem.vhd
.........\instr_mem_vhdl.prj
.........\memtest.tbw
.........\memtest.udo
.........\memtest.xwv
.........\memtest.xwv_bak
.........\mips.ant
.........\mips.fdo
.........\mips.jhd
.........\mips.tbw
.........\mips.udo
.........\mips.vhw
.........\mips.xwv
.........\mips.xwv_bak
.........\mipsfinal.dhp
.........\mipsfinal.ise
.........\mipsfinal.ise_ISE_Backup
.........\mips_bencher.prj
.........\pepExtractor.prj
.........\printfile.vhd
.........\prjname.lso
.........\regtest.tbw
.........\regtest.xwv
.........\regtest.xwv_bak
.........\REG_Block.vhd
.........\results.txt
.........\top.cmd_log
.........\top.lso
.........\top.ngc
.........\top.ngr
.........\top.prj
.........\top.stx
.........\top.syr
.........\top.tbw
.........\top.vhd
.........\top.xwv
.........\top.xwv_bak
.........\top_summary.html
.........\transcript
.........\vsim.wlf
.........\work\alu\alubeh.asm
.........\....\...\alubeh.dat
.........\....\...\_primary.dat
.........\....\...control\aluctrl.asm
.........\....\..........\aluctrl.dat
.........\....\..........\_primary.dat
.........\....\control_unit\behav_ctrl.asm
.........\....\............\behav_ctrl.dat
.........\....\............\_primary.dat
.........\....\data_mem\behav_mem.asm
.........\....\........\behav_mem.dat
.........\....\........\_primary.dat
.........\....\instr_mem\instrbehav.asm
.........\....\.........\instrbehav.dat
.........\....\.........\_primary.dat
.........\....\mips\testbench_arch.asm
.........\....\....\testbench_arch.dat
.........\....\....\_primary.dat
.........\....\reg_block\reg_behav.asm
.........\....\.........\reg_behav.dat
.........\....\.........\_primary.dat
.........\....\top\main.asm
.........\....\...\main.dat
.........\....\...\_primary.dat
.........\....\_info
.........\xst\work\hdllib.ref
.........\...\....\hdpdeps.ref
.........\...\....\sub00\vhpl00.vho
.........\...\....\.....\vhpl01.vho
.........\...\....\.....\vhpl02.vho
.........\...\....\.....\vhpl03.vho
.........\...\....\.....\vhpl04.vho
.........\...\....\.....\vhpl05.vho
.........\...\....\.....\vhpl06.vho
.........\...\....\.....\vhpl07.vho
.........\...\....\.....\vhpl08.vho
.........\...\....\.....\vhpl09.vho
.........\...\....\.....\vhpl10.vho

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