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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 68kb
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  • Author :yan****
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One' s own design, using verilog language implementation of the design of an automatic vending machine
Packet file list
(Preview for download)
mypjct\automatic_sell\smartgen\smartgen.aws
......\..............\hdl\automatic_sell.v
......\..............\...\debouncing.v
......\..............\viewdraw\vf\project.lst
......\..............\........\viewdraw.ini
......\..............\simulation\run.do
......\..............\..........\modelsim.log
......\..............\..........\presynth\_info
......\..............\..........\........\.temp\vlogtd8mtc
......\..............\..........\........\.....\vlog7gz9w4
......\..............\..........\........\_vmake
......\..............\..........\........\automatic_sell\_primary.vhd
......\..............\..........\........\..............\verilog.psm
......\..............\..........\........\..............\_primary.dbs
......\..............\..........\........\..............\_primary.dat
......\..............\..........\........\debouncing\_primary.vhd
......\..............\..........\........\..........\verilog.psm
......\..............\..........\........\..........\_primary.dbs
......\..............\..........\........\..........\_primary.dat
......\..............\..........\........\stimulus\_primary.vhd
......\..............\..........\........\........\verilog.psm
......\..............\..........\........\........\_primary.dbs
......\..............\..........\........\........\_primary.dat
......\..............\..........\........\tb_clock_minmax\_primary.vhd
......\..............\..........\........\...............\verilog.psm
......\..............\..........\........\...............\_primary.dbs
......\..............\..........\........\...............\_primary.dat
......\..............\..........\........\.estbench\_primary.vhd
......\..............\..........\........\.........\verilog.psm
......\..............\..........\........\.........\_primary.dbs
......\..............\..........\........\.........\_primary.dat
......\..............\..........\vsim.wlf
......\..............\..........\modelsim.ini.sav
......\..............\..........\modelsim.ini
......\..............\.ynthesis\stdout.log
......\..............\.........\backup\automatic_sell.srr
......\..............\.........\run_options.txt
......\..............\.........\automatic_sell.tlg
......\..............\.........\automatic_sell.so
......\..............\.........\automatic_sell_syn.prd
......\..............\.........\automatic_sell_syn.prj
......\..............\.........\automatic_sell.srr
......\..............\.timulus\automatic_sell.hpj
......\..............\........\waveperl.log
......\..............\........\BtimErrors.log
......\..............\........\files_to_build.txt
......\..............\........\automatic_sell_tbench.v
......\..............\........\automatic_sell_tbench.btim
......\..............\........\automatic_sell.dsk
......\..............\........\automatic_sell_tbench.bk
......\..............\designer\impl1\automatic_sell.ide_des
......\..............\........\.....\debouncing.ide_des
......\..............\automatic_sell.prj
......\..............\simulation\presynth\_temp
......\..............\..........\........\automatic_sell
......\..............\..........\........\debouncing
......\..............\..........\........\stimulus
......\..............\..........\........\tb_clock_minmax
......\..............\..........\........\testbench
......\..............\designer\impl1\simulation
......\..............\viewdraw\vf
......\..............\........\sch
......\..............\........\sym
......\..............\........\wir
......\..............\simulation\presynth
......\..............\.ynthesis\syntmp
......\..............\.........\coreip
......\..............\.........\backup
......\..............\designer\impl1
......\..............\smartgen
......\..............\hdl
......\..............\constraint
......\..............\viewdraw
......\..............\component
......\..............\coreconsole
......\..............\simulation
......\..............\synthesis
......\..............\phy_synthesis
......\..............\stimulus
......\..............\designer
......\automatic_sell
mypjct
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