Based on xilinx s spartan3a platform electronic clock to implement

Dianzi_Clock\Control_Block.spl
............\Control_Block.sym
............\Control_Block.v
............\device_usage_statistics.html
............\Dianzi_Clock.ise
............\Dianzi_Clock.ise_ISE_Backup
............\Dianzi_Clock.ntrc_log
............\dianzi_clock_top.bgn
............\dianzi_clock_top.bit
............\Dianzi_Clock_Top.bld
............\Dianzi_Clock_Top.cmd_log
............\dianzi_clock_top.drc
............\Dianzi_Clock_Top.jhd
............\Dianzi_Clock_Top.lso
............\Dianzi_Clock_Top.ncd
............\Dianzi_Clock.restore
............\Dianzi_Clock_Top.ngd
............\Dianzi_Clock_Top_map.mrp
............\Dianzi_Clock_Top.pad
............\Dianzi_Clock_Top.par
............\Dianzi_Clock_Top.pcf
............\Dianzi_Clock_Top.prj
............\Dianzi_Clock_Top.sch
............\Dianzi_Clock_Top.schbak
............\Dianzi_Clock_Top.vf
............\Timer_Block.sym
............\Dianzi_Clock_Top.sym
............\Dianzi_Clock_Top.syr
............\dianzi_clock_top.twr
............\dianzi_clock_top.twx
............\Dianzi_Clock_Top.unroutes
............\Dianzi_Clock_Top.ut
............\Dianzi_Clock_Top.v
............\Dianzi_Clock_Top_map.map
............\Dianzi_Clock_Top.xpi
............\Dianzi_Clock_Top.xst
............\Dianzi_Clock_Top_guide.ncd
............\Dianzi_Clock_Top_map.ngm
............\Dianzi_Clock_Top_map.ncd
............\Dianzi_Clock_Top_usage.xml
............\Dianzi_Clock_Top_pad.csv
............\Dianzi_Clock_Top_pad.txt
............\Gen_Clock_10M_10K.sym
............\Dianzi_Clock_Top_prev_built.ngd
............\Dianzi_Clock_Top_summary.html
............\Dianzi_Clock_Top_summary.xml
............\_impact.cmd
............\_impact.log
............\Gen_Clock_10M_10K.spl
............\Lcd_Driver.sym
............\Gen_Clock_10M_10K.v
............\Gen_Clock_66M_10M.spl
............\Gen_Clock_66M_10M.sym
............\Gen_Clock_66M_10M.v
............\Gen_Clock_66M_10M.xaw
............\Gen_Clock_66M_10M_arwz.ucf
............\Lcd_Driver.spl
............\Lcd_Driver.v
............\Limit_IO.ucf
............\Timer_Block.spl
............\Dianzi_Clock_Top.schcmd
............\Timer_Block.v
............\xaw2verilog.log
............\_xmsgs\xst.xmsgs
............\......\ngdbuild.xmsgs
............\......\map.xmsgs
............\......\par.xmsgs
............\......\trce.xmsgs
............\......\bitgen.xmsgs
............\.ngo\netlist.lst
............\xst\work\hdllib.ref
............\...\....\vlg6B\_timer___block.bin
............\...\....\....8\_dianzi___clock___top.bin
............\...\....\...51\_gen___clock__10_m__10_k.bin
............\...\....\...3E\_gen___clock__66_m__10_m.bin
............\...\....\...06\_lcd___driver.bin
............\...\....\....3\_control___block.bin
............\...\dump.xst\Dianzi_Clock_Top.prj\ntrc.scr
............\Dianzi_Clock_Top.ngc
............\Dianzi_Clock_Top.stx
............\Dianzi_Clock_Top.ngr
............\xst\dump.xst\Dianzi_Clock_Top.prj\ngx\opt
............\...\........\....................\...\notopt
............\...\........\....................\ngx
............\...\work\vlg6B
............\...\....\vlg68
............\...\....\vlg51
............\...\....\vlg3E
............\...\....\vlg06
............\...\....\vlg03
............\...\dump.xst\Dianzi_Clock_Top.prj
............\...\work
............\...\projnav.tmp
............\...\dump.xst
............\_xmsgs
............\_ngo
............\xst
Dianzi_Clock

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