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turbodecoder

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 155kb
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  • Author :d*****
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Introduction - If you have any usage issues, please Google them yourself
Using vhdl implementation of iterative decoding turbo codes, transfer of a person' s procedures for N
Packet file list
(Preview for download)
turbo decoder IP core\turbo decoder IP core\doc\LICENSE.txt
.....................\.....................\...\README.txt
.....................\.....................\...\turbo.pdf
.....................\.....................\makeDist
.....................\.....................\src\myhdl\acs.py
.....................\.....................\...\.....\args.py
.....................\.....................\...\.....\clock.py
.....................\.....................\...\.....\coder.py
.....................\.....................\...\.....\distances.py
.....................\.....................\...\.....\extInf.py
.....................\.....................\...\.....\interleaver.py
.....................\.....................\...\.....\iteration.py
.....................\.....................\...\.....\launchTurbo.py
.....................\.....................\...\.....\limiter.py
.....................\.....................\...\.....\misc.py
.....................\.....................\...\.....\noiser.py
.....................\.....................\...\.....\permut.py
.....................\.....................\...\.....\punct.py
.....................\.....................\...\.....\select.py
.....................\.....................\...\.....\sova.py
.....................\.....................\...\.....\synthesis.py
.....................\.....................\...\.....\testbench.py
.....................\.....................\...\.....\trellis.py
.....................\.....................\...\.....\turboTop.py
.....................\.....................\...\vhdl\abPermut_e.vhd
.....................\.....................\...\....\abPermut_synth.vhd
.....................\.....................\...\....\accDistSel_e.vhd
.....................\.....................\...\....\accDistSel_synth.vhd
.....................\.....................\...\....\accDist_e.vhd
.....................\.....................\...\....\accDist_synth.vhd
.....................\.....................\...\....\acs_e.vhd
.....................\.....................\...\....\acs_synth.vhd
.....................\.....................\...\....\adder_e.vhd
.....................\.....................\...\....\adder_synth.vhd
.....................\.....................\...\....\clkDiv_e.vhd
.....................\.....................\...\....\clkDiv_synth.vhd
.....................\.....................\...\....\clkrst_beh.vhd
.....................\.....................\...\....\clkrst_e.vhd
.....................\.....................\...\....\cmp2_e.vhd
.....................\.....................\...\....\cmp2_synth.vhd
.....................\.....................\...\....\cod2_e.vhd
.....................\.....................\...\....\cod2_synth.vhd
.....................\.....................\...\....\cod3_e.vhd
.....................\.....................\...\....\cod3_synth.vhd
.....................\.....................\...\....\coder_e.vhd
.....................\.....................\...\....\coder_synth.vhd
.....................\.....................\...\....\delayer_e.vhd
.....................\.....................\...\....\delayer_synth.vhd
.....................\.....................\...\....\distances_e.vhd
.....................\.....................\...\....\distances_synth.vhd
.....................\.....................\...\....\distance_e.vhd
.....................\.....................\...\....\distance_synth.vhd
.....................\.....................\...\....\extInf_e.vhd
.....................\.....................\...\....\extInf_synth.vhd
.....................\.....................\...\....\interleaver_e.vhd
.....................\.....................\...\....\interleaver_synth.vhd
.....................\.....................\...\....\iteration_e.vhd
.....................\.....................\...\....\iteration_synth.vhd
.....................\.....................\...\....\limiter_e.vhd
.....................\.....................\...\....\limiter_synth.vhd
.....................\.....................\...\....\min4_e.vhd
.....................\..................
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