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sdram_control.RAR

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 3.52mb
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  • Author :bigch*****
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SDRAM CONTROLER
Packet file list
(Preview for download)
sdram_control\src\Command.v
.............\...\control_interface.v
.............\...\datacnl.v.bak
.............\...\Params.v
.............\...\sdram_test_tb.v.bak
.............\...\sdr_data_path.v
.............\...\sdr_sdram.v
.............\src
.............\.im\altera_mf.v
.............\...\mt48lc2m32b2.v
.............\...\Params.v
.............\...\sdram_test.wlf
.............\...\sdram_test_tb.v
.............\...\sdram_test_tb.v.bak
.............\...\work\_info
.............\...\....\stx_scale_cntr\verilog.asm
.............\...\....\..............\_primary.dat
.............\...\....\..............\_primary.vhd
.............\...\....\stx_scale_cntr
.............\...\....\....n_cntr\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\stx_n_cntr
.............\...\....\....m_cntr\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\stx_m_cntr
.............\...\....\..ratix_lvds_rx\verilog.asm
.............\...\....\...............\_primary.dat
.............\...\....\...............\_primary.vhd
.............\...\....\stratix_lvds_rx
.............\...\....\.......ii_tx_outclk\verilog.asm
.............\...\....\...................\_primary.dat
.............\...\....\...................\_primary.vhd
.............\...\....\stratixii_tx_outclk
.............\...\....\..........lvds_rx\verilog.asm
.............\...\....\.................\_primary.dat
.............\...\....\.................\_primary.vhd
.............\...\....\stratixii_lvds_rx
.............\...\....\.......gx_dpa_lvds_rx\verilog.asm
.............\...\....\.....................\_primary.dat
.............\...\....\.....................\_primary.vhd
.............\...\....\stratixgx_dpa_lvds_rx
.............\...\....\.dr_sdram\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\sdr_sdram
.............\...\....\....data_path\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\sdr_data_path
.............\...\....\...am_test_tb\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\sdram_test_tb
.............\...\....\.cfifo\verilog.asm
.............\...\....\......\_primary.dat
.............\...\....\......\_primary.vhd
.............\...\....\scfifo
.............\...\....\parallel_add\verilog.asm
.............\...\....\............\_primary.dat
.............\...\....\............\_primary.vhd
.............\...\....\parallel_add
.............\...\....\mt48lc2m32b2\verilog.asm
.............\...\....\............\_primary.dat
.............\...\....\............\_primary.vhd
.............\...\....\mt48lc2m32b2
.............\...\....\lcell\verilog.asm
.............\...\....\.....\_primary.dat
.............\...\....\.....\_primary.vhd
.............\...\....\lcell
.............\...\....\hssi_tx\verilog.asm
.............\...\....\.......\_primary.dat
.............\...\....\.......\_primary.vhd
.............\...\....\hssi_tx
.............\...\....\.....rx\verilog.asm
.............\...\....\.......\_primary.dat
.............\...\....\.......\_primary.vhd
.............\...\....\hssi_rx
.............\...\....\.....pll\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\hssi_pll
.............\...\....\.....fifo\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\hssi_fifo
.............\...\....\global\verilog.asm
.............\...\....\......\_primary.dat
.............\...\....\......\_primary.vhd
.............\...\....\global
.............\...\....\exp\verilog.asm
.............\...\....\...\_primary.dat
.............\...\....\...\_primary.vhd
.............\...\....\exp
.............\...\....\dffp\verilog.asm
.............\...\....\....\_primary.dat
..
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