The document is a complete project file, with VerilogHDL languages, including the Manchester encoder design documents and simulation test files and decoder design documents and simulation test file. In the Modelsim simulation test.

4.2\manch_de.rpt
...\manch_de.v
...\manch_de_testbench.v
...\manch_en.rpt
...\manch_en.v
...\manch_en_de.cr.mti
...\manch_en_de.mpf
...\manch_en_de.v
...\manch_en_testbench.v
...\transcript
...\vsim.wlf
...\chart\Thumbs.db
...\.....\图4-5.bmp
...\.....\图4-7.bmp
...\wave\Thumbs.db
...\....\manch_de.bmp
...\....\manch_de_testbench.bmp
...\....\manch_en.bmp
...\....\manch_en_testbench.bmp
...\.ork\_info
...\....\manch_de\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\......en\_primary.dat
...\....\........\_primary.vhd
...\....\........\verilog.asm
...\....\........_de\_primary.dat
...\....\...........\_primary.vhd
...\....\...........\verilog.asm
...\....\.........testbench\_primary.dat
...\....\..................\_primary.vhd
...\....\..................\verilog.asm
...\....\manch_de
...\....\manch_de_testbench
...\....\manch_en
...\....\manch_en_de
...\....\manch_en_testbench
...\chart
...\wave
...\work
4.2

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