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VHDLdigital

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
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  • Author :爱***
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7 digital control design and implementation of the decoder 1. Purpose of the experiment 1. To master digital control decoder 7 Design and Implementation 2. Master modular design 2. Experimental content Design of a 7-segment digital tube decoder, with a digital 4-bit reversible counter tube [Specific requirements] 1.7 Duan digital control decoder Use DIP switch SW3, SW2, SW1, SW0 as input, SW3 is high, SW0 is low. The output of the HEX1, HEX0 display. When the input to 0000 ~ 1111 is displayed as 00 to 15, 2. With digital control of the 4-bit reversible counter The experimental results of the three digital tube display. Combined with the previous experiment, the 4-bit reversible counter, digital display, as the two sub-modules, respectively, to achieve in the digital tube display reversible 4-bit counter.
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udcounter.vhd
数码管.docx
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