Introduction - If you have any usage issues, please Google them yourself
Verilog写的简单处理器QuartusII下可编译
//指令 操作码 源寄存器 目的寄存器 操作
// NOP 0000 xxxxx xxxxxx 空操作
//ADD 0001 src dest dest<=src+dest
//SUB 0010 src dest dest<=dest-src
//AND 0011 src dest dest<=src&&dest
//NOT 0100 src dest dest<=~src
//RD 0101 xxxxx dest dest<= memory[Add_R]
//WR 0110 src xxxxx memory[Add_R]<=src
//BR 0111 xxxxx xxxxx PC<=memory[Add_R]
//BRZ 1000 xxxxx xxxxx PC<=memory[Add_R]
//HALT 1111 xxxxx xxxxx 挂起至RST