It is mainly used to achieve the control of reading and writing of nand flash memory in FPGA. It is mainly used to achieve control of read and write nand flash memory control, is the company website

Data_switch_project.ise
Data_switch_project.ise_ISE_Backup
isim
....\simprim.auxlib
....\..............\hdllib.ref
....\..............\vcomponents
....\..............\...........\mingw
....\..............\...........\.....\vcomponents.obj
....\..............\...........\vcomponents.h
....\..............\vpackage
....\..............\........\mingw
....\..............\........\.....\vpackage.obj
....\..............\........\vpackage.h
....\..............\x_and2
....\..............\......\mingw
....\..............\......\.....\x_and2_v.obj
....\..............\......\x_and2_v.h
....\..............\x_and3
....\..............\......\mingw
....\..............\......\.....\x_and3_v.obj
....\..............\......\x_and3_v.h
....\..............\x_and4
....\..............\......\mingw
....\..............\......\.....\x_and4_v.obj
....\..............\......\x_and4_v.h
....\..............\x_buf
....\..............\.....\mingw
....\..............\.....\.....\x_buf_v.obj
....\..............\.....\x_buf_v.h
....\..............\x_inv
....\..............\.....\mingw
....\..............\.....\.....\x_inv_v.obj
....\..............\.....\x_inv_v.h
....\..............\x_or2
....\..............\.....\mingw
....\..............\.....\.....\x_or2_v.obj
....\..............\.....\x_or2_v.h
....\..............\x_or3
....\..............\.....\mingw
....\..............\.....\.....\x_or3_v.obj
....\..............\.....\x_or3_v.h
....\..............\x_roc
....\..............\.....\mingw
....\..............\.....\.....\x_roc_v.obj
....\..............\.....\x_roc_v.h
....\..............\x_tri
....\..............\.....\mingw
....\..............\.....\.....\x_tri_v.obj
....\..............\.....\x_tri_v.h
....\..............\x_xor2
....\..............\......\mingw
....\..............\......\.....\x_xor2_v.obj
....\..............\......\x_xor2_v.h
....\..............\x_zero
....\..............\......\mingw
....\..............\......\.....\x_zero_v.obj
....\..............\......\x_zero_v.h
....\work
....\....\hdllib.ref
....\....\hdpdeps.ref
....\....\sub00
....\....\.....\vhpl00.vho
....\....\.....\vhpl01.vho
....\....\.....\vhpl02.vho
....\....\.....\vhpl03.vho
....\....\ts_switch
....\....\.........\mingw
....\....\.........\.....\structure.obj
....\....\.........\structure.h
....\....\ts_switch_testbench
....\....\...................\mingw
....\....\...................\.....\testbench_arch.obj
....\....\...................\testbench_arch.h
....\....\...................\xsimtestbench_arch.cpp
isim.cmd
isim.hdlsourcefiles
isim.log
isim.tmp_save
.............\_1
isimwavedata.xwv
netgen
......\fit
......\...\TS_switch_timesim.nlf
......\...\TS_switch_timesim.sdf
......\...\TS_switch_timesim.vhd
pepExtractor.prj
results.txt
tmperr.err
tmpRTVStore.xwv
Transport_stream_switch.vhd
TS_switch.bld
TS_switch.chk
TS_switch.cmd_log
TS_switch.cxt
TS_switch.data
TS_switch.gyd
TS_switch.log
TS_switch.lso
TS_switch.mfd
TS_switch.mod

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