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VHDL-FPGA-Verilog
- Category : VHDL-FPGA-Verilog
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- Update : 2012-11-26
- Size : 218kb
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- Author ：陳****
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Introduction - If you have any usage issues, please Google them yourself
proposes a Verilog implementation of the
Normalized Least Mean Square (NLMS) adaptive algorithm,
having a variable step size. The envisaged application is the
identification of an unknown system. First the convergence of
derived LMS algorithms was analyzed in a Simulink application.
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(Preview for download)
HDLImplementationoftheVariableStepSize.pdf
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