Through the simulation of the VHDL program downloaded to the FPGA chip EPF10K10LC84-3, the obtained satisfactory results. The design choices (3,1,2) convolutional code and (2,1,1) convolutional code, are highly representative of convolutional codes. For convolutional codes with similar structure and characteristics, so (3,1,2) convolutional encoder and (2,1,1) convolutional decoder design has general applicability.

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