The source code for the FPGA-based FLASH memory using the VERILOG prepared to read and write procedures.

flash\altpll1.bsf
.....\altpll1.cmp
.....\altpll1.inc
.....\altpll1.ppf
.....\altpll1.v
.....\altpll1_bb.v
.....\altpll1_inst.v
.....\altpll1_wave0.jpg
.....\altpll1_waveforms.html
.....\clock_1khz.bsf
.....\clock_1khz.v
.....\flash.bsf
.....\flash.v
.....\flash_project.asm.rpt
.....\flash_project.bdf
.....\flash_project.cdf
.....\flash_project.done
.....\flash_project.fit.rpt
.....\flash_project.fit.smsg
.....\flash_project.fit.summary
.....\flash_project.flow.rpt
.....\flash_project.map.rpt
.....\flash_project.map.smsg
.....\flash_project.map.summary
.....\flash_project.pin
.....\flash_project.pof
.....\flash_project.qpf
.....\flash_project.qsf
.....\flash_project.sim.rpt
.....\flash_project.sof
.....\flash_project.stp
.....\flash_project.tan.rpt
.....\flash_project.tan.summary
.....\flash_project.vwf
.....\nios_1.bsf
.....\nios_1.v
.....\serial.bsf
.....\serial.v
.....\db\altsyncram_3ki2.tdf
.....\..\altsyncram_5ki2.tdf
.....\..\altsyncram_7ki2.tdf
.....\..\altsyncram_9ki2.tdf
.....\..\altsyncram_pji2.tdf
.....\..\cmpr_7mh.tdf
.....\..\cntr_5jf.tdf
.....\..\cntr_6ag.tdf
.....\..\cntr_bhe.tdf
.....\..\cntr_e7f.tdf
.....\..\cntr_hhe.tdf
.....\..\cntr_ihe.tdf
.....\..\cntr_khe.tdf
.....\..\cntr_lhe.tdf
.....\..\cntr_odh.tdf
.....\..\decode_ogi.tdf
.....\..\flash_project.sim.vwf
.....\..\wed.zsf
.....\..\flash_project.db_info
.....\..\flash_project.sld_design_entry.sci
.....\..\flash_project.eco.cdb
.....\flash_project_assignment_defaults.qdf
.....\flash_project.qws
.....\db
flash

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