Introduction - If you have any usage issues, please Google them yourself
lattice sdram controller source code, including VHDL simulation document coding
Packet : 85375566lattice_sdram_source_code.zip filelist
Source/
Source/CPLD_Verilog/
Source/CPLD_Verilog/sdr_5kvg_top.v
Source/CPLD_Verilog/sdr_ctrl.v
Source/CPLD_Verilog/sdr_data.v
Source/CPLD_Verilog/sdr_par.v
Source/CPLD_Verilog/sdr_sig.v
Source/CPLD_Verilog/sdr_top.v
Source/EC_Verilog/
Source/EC_Verilog/sdr_ctrl.v
Source/EC_Verilog/sdr_data.v
Source/EC_Verilog/sdr_par.v
Source/EC_Verilog/sdr_sig.v
Source/EC_Verilog/sdr_top.v
Testbench/
Testbench/CPLD_Verilog/
Testbench/CPLD_Verilog/sdr_5kvg_tb.tf
Testbench/CPLD_Verilog/sdr_tb.tf
Testbench/EC_Verilog/
Testbench/EC_Verilog/sdr_tb.tf