`timescale 1ns/1ns module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout) input clk_wr,wr_en,clk_rd,rd_en,rst input[7:0] din output full,empty output[7:0] dout reg full_temp,empty_temp,full_temp1,empty_temp1 wire full,empty wire[7:0] dout reg[9:0] cnt_wr,cnt_rd,encode_cnt_wr,encode_cnt_rd wire[9:0] gray_cnt_wr,gray_cnt_rd integer i reg[9:0] encode_a,encode_b,tempa,tempb

视频图像捕获系统SRAM控制器的FPGA实现.pdf

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．