Using the Verilog language point FFT, 64, and includes test files, in addition to FFT, a summary document.

64point_FFT\64-point_Radix4_Pipeline_FFT.doc
...........\output\fft64_top.sdc
...........\......\fft64_top.v
...........\......\fft64_top10.sdc
...........\......\fft64_top10.v
...........\report\fft64_area.rpt
...........\......\fft64_area10.rpt
...........\......\fft64_power10.rpt
...........\......\fft64_timing.rpt
...........\......\fft64_timing10.rpt
...........\......\fft64_top
...........\......\fft64_top.rpt
...........\......\fft64_top10.rpt
...........\scripts\constraint.tcl
...........\.......\fft_top.tcl
...........\.......\read_src.tcl
...........\.rc\ALU1.v
...........\...\ALU2.v
...........\...\booth10_multiplier.v
...........\...\booth10_multiplier.v~
...........\...\booth10_partial_product.v
...........\...\booth10_partial_product.v~
...........\...\bu4_st1.v
...........\...\bu4_st2.v
...........\...\bu4_st3.v
...........\...\coef_rom_st1.v
...........\...\coef_rom_st2.v
...........\...\fft4_st1.v
...........\...\fft4_st2.v
...........\...\fft64_top.v
...........\...\out_index.v
...........\...\random_gen.v
...........\...\regbank_16.v
...........\...\regbank_4.v
...........\...\test\fft64_out_im.txt
...........\...\....\fft64_out_re.txt
...........\...\....\rand_13_bit.txt
...........\...\....\rand_16_bit.txt
...........\...\....\tb_fft64_top.v
...........\...\twd_fac_multiplier10.v
...........\...\test
...........\output
...........\report
...........\scripts
...........\src
64point_FFT

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