The verilog code for control ADV7123 with FPGA.

VGA_Pattern
...........\db
...........\..\prev_cmp_VGA_Pattern.map.qmsg
...........\..\prev_cmp_VGA_Pattern.qmsg
...........\..\VGA_Pattern.cbx.xml
...........\..\VGA_Pattern.cmp.rdb
...........\..\VGA_Pattern.db_info
...........\..\VGA_Pattern.eco.cdb
...........\..\VGA_Pattern.hier_info
...........\..\VGA_Pattern.hif
...........\..\VGA_Pattern.map.bpm
...........\..\VGA_Pattern.map.cdb
...........\..\VGA_Pattern.map.ecobp
...........\..\VGA_Pattern.map.hdb
...........\..\VGA_Pattern.map.logdb
...........\..\VGA_Pattern.map.qmsg
...........\..\VGA_Pattern.map_bb.cdb
...........\..\VGA_Pattern.map_bb.hdb
...........\..\VGA_Pattern.map_bb.hdbx
...........\..\VGA_Pattern.map_bb.logdb
...........\..\VGA_Pattern.pre_map.cdb
...........\..\VGA_Pattern.pre_map.hdb
...........\..\VGA_Pattern.psp
...........\..\VGA_Pattern.root_partition.map.atm
...........\..\VGA_Pattern.root_partition.map.hdbx
...........\..\VGA_Pattern.root_partition.map.info
...........\..\VGA_Pattern.rpp.qmsg
...........\..\VGA_Pattern.rtlv.hdb
...........\..\VGA_Pattern.rtlv_sg.cdb
...........\..\VGA_Pattern.rtlv_sg_swap.cdb
...........\..\VGA_Pattern.sgate.rvd
...........\..\VGA_Pattern.sgate_sm.rvd
...........\..\VGA_Pattern.sgdiff.cdb
...........\..\VGA_Pattern.sgdiff.hdb
...........\..\VGA_Pattern.sld_design_entry.sci
...........\..\VGA_Pattern.sld_design_entry_dsc.sci
...........\..\VGA_Pattern.syn_hier_info
...........\..\VGA_Pattern.tis_db_list.ddb
...........\v
...........\VGA_Pattern.done
...........\VGA_Pattern.flow.rpt
...........\VGA_Pattern.map.rpt
...........\VGA_Pattern.map.summary
...........\VGA_Pattern.qpf
...........\VGA_Pattern.qsf
...........\VGA_Pattern.qws
...........\v\VGA_Pattern.v
...........\.\VGA_Pattern.v.bak

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