Eight-phase shift keying modulation of the Verilog program, each module is given the procedures, the signal modulation.

BPSK\arrange_data.v
....\cic_4_dec.v
....\cic_inter_step1.v
....\cic_4_dec.v.bak
....\cic_inter_step1.v.bak
....\div_clock.v
....\mydds_mod.v
....\clk_dcm_130m.v
....\fifo_asyn_rrc.v
....\i_filter.v
....\arrange_data.v.bak
....\fifo_asyn_rrc.v.bak
....\mydds_mod.v.bak
....\i_filter.v.bak
....\8_modulate.v.bak
....\b_8_modulate.v
....\modulate_8psk_tf.v
....\b_8_modulate.v.bak
....\modulate_8psk_tf.v.bak
....\ASYNC_FIFO_V5_1.v
....\C_DA_FIR_V8_0.v
....\DCM.v
....\clk_dcm_26m.v
....\clk_dcm_975m.v
....\clk_dcm_26m.v.bak
....\mix_up.v
....\mix_up.v.bak
....\clk_dcm_975m.v.bak
....\BUFG.v
....\IBUFG.v
....\RomSin.v
....\RomCos.v
....\复件 b_8_modulate.v
....\复件 arrange_data.v
BPSK

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