This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.

SD_Controller_Verilog\bench\sdc_dma\verilog\sdModel.v
.....................\.....\.......\.......\SD_controller_top_tb.v
.....................\.....\.......\.......\timescale.v
.....................\.....\.......\.......\transcript
.....................\.....\.......\.......\wb_bus_mon.v
.....................\.....\.......\.......\wb_master32.v
.....................\.....\.......\.......\wb_master_behavioral.v
.....................\.....\.......\.......\wb_model_defines.v
.....................\.....\.......\.......\wb_slave_behavioral.v
.....................\doc\Design SDC_MMC controller.pdf
.....................\...\References\Simplified_Physical_Layer_Spec-1.pdf
.....................\...\Specification SDC_MMC controller.pdf
.....................\rtl\sdc_dma\verilog\Makefile
.....................\...\.......\.......\SD_Bd.v
.....................\...\.......\.......\SD_clock_divider.v
.....................\...\.......\.......\SD_cmd_master.v
.....................\...\.......\.......\SD_cmd_serial_host.v
.....................\...\.......\.......\SD_controller_top.v
.....................\...\.......\.......\SD_controller_wb.v
.....................\...\.......\.......\SD_crc_16.v
.....................\...\.......\.......\SD_crc_7.v
.....................\...\.......\.......\SD_data_host.v
.....................\...\.......\.......\SD_data_master.v
.....................\...\.......\.......\SD_defines.v
.....................\...\.......\.......\SD_FIFO_RX_Filler.v
.....................\...\.......\.......\SD_FIFO_TX_Filler.v
.....................\...\....fifo\verilog\Makefile
.....................\...\........\.......\sd_cmd_phy.v
.....................\...\........\.......\sd_controller_fifo_actel.v
.....................\...\........\.......\sd_controller_fifo_wb.v
.....................\...\........\.......\sd_counter.v
.....................\...\........\.......\sd_crc_16.v
.....................\...\........\.......\sd_crc_7.v
.....................\...\........\.......\sd_data_phy.v
.....................\...\........\.......\sd_defines.v
.....................\...\........\.......\sd_fifo.v
.....................\...\........\.......\sd_ip_comp_inst.v
.....................\...\........\.......\versatile_fifo_async_cmp.v
.....................\...\........\.......\versatile_fifo_dptam_dw.v
.....................\sim\rtl_sim\bin\FLASH.txt
.....................\...\.......\...\wb_memory.txt
.....................\...\.......\log\eth_tb_host.log
.....................\...\.......\...\eth_tb_phy.log
.....................\...\.......\...\eth_tb_wb_m_mon.log
.....................\...\.......\...\eth_tb_wb_s_mon.log
.....................\...\.......\...\sdc_tb.log
.....................\...\.......\...\sd_model.log
.....................\...\.......\...\sd_tb_memory.log
.....................\...\.......\run\comp.do
.....................\...\.......\...\log\eth_tb_host.log
.....................\...\.......\...\...\eth_tb_phy.log
.....................\...\.......\...\...\eth_tb_wb_m_mon.log
.....................\...\.......\...\...\eth_tb_wb_s_mon.log
.....................\...\.......\...\...\sdc_tb.log
.....................\...\.......\...\...\sd_model.log
.....................\...\.......\...\...\sd_tb_memory.log
.....................\...\.......\...\work\_info
.....................\...\.......\...\....\.temp\vlog086ftz
.....................\.w\sdc_dma\board.h
.....................\..\.......\BootReset.S
.....................\..\.......\BootReset.S.lowram
.....................\..\.......\main.c
.....................\..\.......\orsocdef.h
.....................\..\.......\ram.ld
.....................\..\.......\sd_controller.c
.....................\..\.......\sd_controller.h
.....................\..\.......\spr_defs.h
.....................\..\.......\uart.c
.....................\..\.......\uart.h
.....................\..\....fifo\main.c
.....................\.im\rtl_sim\run\work\_temp
.....................\...\.......\...\log
.....................\...\.......\...\work
.....................\bench\sdc_dma\verilog
.....................\rtl\sdc_dma\

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