DDR2 controller which contains verilog files，pdf and so on

DDR2_Memory_Test\BitFiles\DDR2_Memory_Test.bit
................\........\DDR2_Memory_Test_Error_Confirm.cpj
................\Chipscope\small_icon.edn
................\.........\small_icon.ncf
................\.........\small_icon.ngo
................\.........\small_ila.edn
................\.........\small_ila.ncf
................\.........\small_ila.ngo
................\Readme.txt
................\Ucf\ML555_DDR2_Memory_Test.ucf
................\Verilog\mem.v
................\.......\mem_ctrl_0.v
................\.......\mem_idelay_ctrl.v
................\.......\mem_infrastructure.v
................\.......\mem_parameters_0.v
................\.......\mem_phy_0.v
................\.......\mem_phy_calib_0.v
................\.......\mem_phy_ctl_io_0.v
................\.......\mem_phy_dm_iob.v
................\.......\mem_phy_dqs_iob.v
................\.......\mem_phy_dq_iob.v
................\.......\mem_phy_init_0.v
................\.......\mem_phy_io_0.v
................\.......\mem_phy_write_0.v
................\.......\mem_RAM_D_0.v
................\.......\mem_test_bench_0.v
................\.......\mem_test_cmp_0.v
................\.......\mem_test_rom_0.v
................\.......\mem_test_rom_addr_0.v
................\.......\mem_test_rom_data_16.v
................\.......\mem_test_rom_data_8.v
................\.......\mem_top_0.v
................\.......\mem_usr_0.v
................\.......\mem_usr_ip_addr_fifo_0.v
................\.......\mem_usr_ip_fifos_0.v
................\.......\mem_usr_ip_wr_fifo_16.v
................\.......\mem_usr_ip_wr_fifo_8.v
................\.......\mem_usr_rd_0.v
................\.......\mem_usr_rd_fifo_0.v
................\BitFiles
................\Chipscope
................\Ucf
................\Verilog
DDR2_Memory_Test

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