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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 36kb
  • Downloaded :0次
  • Author :man***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
linijka--pomiarowa.rar Generalnie w odbiorniku nie ma wiekszel filozofi. Sa sygnaly z 2 czujnikow, zaluzmy ze czujnik 1 jest po lewej stronie, 2 po prawej. Czyli (zgodnie z tym opisem www.elektroda.pl/rtvforum/topic1132763.html) jeli z 2-giego czujnika dochodzi sygnal wysoki a na 1 pojawia sie zbocze narastajace to wykrywany jest ruch w prawo o 1 krok (jednostke) - odwrotnie dla drugiego (1 stan wysoki, 2 zbocze narastajace to ruch w lewo). Uklad jest taktowany zegarem 60 MHz (dlatego ze maksymalna czestotliwosc wykrywanych impulsow z czujnikow to 30MHz, tak wiec czestotliwosc ukladu powinna byc 2 razy wieksza - ale to moze pan dopytac najwyzej prowadzecego). Jest modul test ktory zadaje wymuszenia (sekwencje impulsow dla ruchu w prwo i wlewo i sprawdza odpowiedz)
Packet file list
(Preview for download)
linijka\odbiornik.vhd
.......\odbiornik_impulsow.cr.mti
.......\odbiornik_impulsow.mpf
.......\transcript
.......\vsim.wlf
.......\wave.do
.......\.ork\odbiornik_impulsow\arch.dat
.......\....\..................\arch.psm
.......\....\..................\_primary.dat
.......\....\test\test_arch.dat
.......\....\....\test_arch.psm
.......\....\....\_primary.dat
.......\....\.op\top_arch.dat
.......\....\...\top_arch.psm
.......\....\...\_primary.dat
.......\....\_info
.......\....\odbiornik_impulsow
.......\....\test
.......\....\top
.......\work
linijka
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