The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.

mul_ser12\basic_mul12.acf
.........\basic_mul12.fit
.........\basic_mul12.hex
.........\basic_mul12.hif
.........\basic_mul12.mmf
.........\basic_mul12.ndb
.........\basic_mul12.pin
.........\basic_mul12.pof
.........\basic_mul12.rpt
.........\basic_mul12.scf
.........\basic_mul12.snf
.........\basic_mul12.sof
.........\basic_mul12.ttf
.........\basic_mul12.v
.........\LIB.DLS
.........\mul_ser12.acf
.........\mul_ser12.fit
.........\mul_ser12.hex
.........\mul_ser12.hif
.........\mul_ser12.mmf
.........\mul_ser12.ndb
.........\mul_ser12.pin
.........\mul_ser12.pof
.........\mul_ser12.rpt
.........\mul_ser12.scf
.........\mul_ser12.snf
.........\mul_ser12.sof
.........\mul_ser12.ttf
.........\mul_ser12.v
.........\U0878453.DLS
.........\U1385387.DLS
.........\U9466381.DLS
mul_ser12

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