Introduction - If you have any usage issues, please Google them yourself
last time when i came here to find some clock references. but most of them can not works well. so this works well on files FPGA board.
Packet : 5956488rtl.zip filelist
clk_gen.vhd
counter.vhd
program-h.vhd
program-m.vhd
program-s.vhd
seg.vhd
six choose one.vhd
top_test.vhd