DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.

sixiangzaibosheji\pll.v
.................\sine.v
.................\sine_rom.v
sixiangzaibosheji

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