Verilog written with motion-adaptive deinterlacing algorithm detects the edge of the table to expand the minimum write sad

MODELSYS\50帧处理后的数据导出\datao_yuyv_50f.txt
........\....................\datao_y_50f.txt
........\FLS数据到SRAM.bmp
........\NEWSYS\atera\_info
........\......\datao_vu_1flog.log
........\......\datao_vu_50f.txt
........\......\datao_yuyv_1flog.log
........\......\datao_yuyv_50f.txt
........\......\datao_y_1flog.log
........\......\datao_y_50f.txt
........\......\.einterlace\average.v
........\......\...........\average.v.bak
........\......\...........\deinterlace.v
........\......\...........\deinterlace.v.bak
........\......\...........\deintertop.v
........\......\...........\diffmin_new.v
........\......\...........\diffmin_new.v.bak
........\......\...........\juedui.v
........\......\...........\median.v
........\......\...........\minl.v
........\......\flash\am29lv256m.v
........\......\.....\am29lv256m.v.bak
........\......\.....\flashctrl_modify.v
........\......\.....\flashctrl_modify.v.bak
........\......\.....\flashctrl_TOP.v
........\......\.....\flashctrl_TOP.v.bak
........\......\.....\flashrom.v
........\......\.....\flashrom.v.bak
........\......\.....\flash_package.v
........\......\.....\flash_package.v.bak
........\......\foreman_yvyu50f.mem
........\......\foreman_yvyu50f.txt
........\......\framebuf.v
........\......\framebuf.v.bak
........\......\lineadr_let\lineadr_let.v
........\......\...........\lineadr_let.v.bak
........\......\....buf\aftwdram.v
........\......\.......\downram.v
........\......\.......\fwdram.v
........\......\.......\linebuf.v
........\......\.......\upram.v
........\......\lineread.v
........\......\lineread.v.bak
........\......\mainctrl.v
........\......\MODEL2DIS\data_wrtsel.v
........\......\.........\data_wrtsel.v.bak
........\......\.........\data_wrtselTB.v
........\......\.........\data_wrtselTB.v.bak
........\......\.........\display_ram0.v
........\......\.........\display_ram0.v.bak
........\......\.........\displsy_ram1.v
........\......\.........\displsy_ram1.v.bak
........\......\model_TB.v
........\......\model_TB.v.bak
........\......\model_TOP.v
........\......\model_TOP.v.bak
........\......\NEWSYSmodel.cr.mti
........\......\NEWSYSmodel.mpf
........\......\parameter.v
........\......\rbtbuf\rbtbuf.v
........\......\......\rbtram1.v
........\......\......\rbtram2.v
........\......\......\rbtram3.v
........\......\......\rbtram4.v
........\......\sram\IS61LV25616.v
........\......\....\IS61LV25616.v.bak
........\......\....\sram.cr.mti
........\......\....\sram.mpf
........\......\....\sramctrl.v
........\......\....\sramctrl.v.bak
........\......\....\srampackage.v
........\......\....\srampackage.v.bak
........\......\....\srampackage_TB.v
........\......\....\srampackage_TB.v.bak
........\......\....\sram_control.v.bak
........\......\....\vsim.wlf
........\......\....\work\@i@s61@l@v25616\verilog.asm
........\......\....\....\...............\_primary.dat
........\......\....\....\...............\_primary.vhd
........\......\....\....\srampackage\verilog.asm
........\......\....\....\...........\_primary.dat
........\......\....\....\...........\_primary.vhd
........\......\....\....\..........._@t@b\verilog.asm
........\......\....\....\................\_primary.dat
........\......\....\....\................\_primary.vhd
........\......\....\....\...._control\verilog.asm
........\......\....\....\............\_primary.dat
........\......\....\....\............\_primary.vhd
........\......\....\....\_info
........\......\timescale.v
........\......\transcript
........\......\vga_dis\rbgdisplay.v.bak
........\......\.......\VGA_test1\vgainterface\akiyo300_1ref.mif
........\......\.......\.........\............\Chain1.cdf
........\......\.......\.........\............\cmp_state.ini
........\......\.......\.........\............\datao_yvyu_3f.hex
........\......\.......\.........\............\datao_yvyu_3f.mif
........\......\.......\.........\............\.b\add_sub_hsh.tdf
........\......\.......\.........\............\..\add_sub_ish.tdf
........\......\.......\.........\............\..\altsyncram_0q81.tdf

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