Introduction - If you have any usage issues, please Google them yourself
using VHDL description of 7 degrees LED digital display tubes, which were developed in FPGA
Packet : 13898396led.rar filelist
7段LED\db\DECL7S.(0).cnf.cdb
7段LED\db\DECL7S.(0).cnf.hdb
7段LED\db\DECL7S.asm.qmsg
7段LED\db\DECL7S.cbx.xml
7段LED\db\DECL7S.cmp.cdb
7段LED\db\DECL7S.cmp.hdb
7段LED\db\DECL7S.cmp.qrpt
7段LED\db\DECL7S.cmp.rdb
7段LED\db\DECL7S.cmp.tdb
7段LED\db\DECL7S.cmp0.ddb
7段LED\db\DECL7S.dbp
7段LED\db\DECL7S.db_info
7段LED\db\DECL7S.eco.cdb
7段LED\db\DECL7S.fit.qmsg
7段LED\db\DECL7S.hier_info
7段LED\db\DECL7S.hif
7段LED\db\DECL7S.map.cdb
7段LED\db\DECL7S.map.hdb
7段LED\db\DECL7S.map.qmsg
7段LED\db\DECL7S.pre_map.cdb
7段LED\db\DECL7S.pre_map.hdb
7段LED\db\DECL7S.psp
7段LED\db\DECL7S.rpp.qmsg
7段LED\db\DECL7S.rtlv.hdb
7段LED\db\DECL7S.rtlv_sg.cdb
7段LED\db\DECL7S.rtlv_sg_swap.cdb
7段LED\db\DECL7S.sgate.rvd
7段LED\db\DECL7S.sgate_sm.rvd
7段LED\db\DECL7S.sgdiff.cdb
7段LED\db\DECL7S.sgdiff.hdb
7段LED\db\DECL7S.signalprobe.cdb
7段LED\db\DECL7S.sld_design_entry.sci
7段LED\db\DECL7S.sld_design_entry_dsc.sci
7段LED\db\DECL7S.syn_hier_info
7段LED\db\DECL7S.tan.qmsg
7段LED\DECL7S.asm.rpt
7段LED\DECL7S.bsf
7段LED\DECL7S.done
7段LED\DECL7S.fit.eqn
7段LED\DECL7S.fit.rpt
7段LED\DECL7S.fit.summary
7段LED\DECL7S.flow.rpt
7段LED\DECL7S.map.eqn
7段LED\DECL7S.map.rpt
7段LED\DECL7S.map.summary
7段LED\DECL7S.pin
7段LED\DECL7S.pof
7段LED\DECL7S.qpf
7段LED\DECL7S.qsf
7段LED\DECL7S.qws
7段LED\DECL7S.sof
7段LED\DECL7S.tan.rpt
7段LED\DECL7S.tan.summary
7段LED\DECL7S.vhd
7段LED\db
7段LED