rs232 code with verilog has been verified

uart_fpga4fun\.lso
.............\async_receiver_summary.html
.............\clk_gen.v
.............\clk_gen_summary.html
.............\impact.xsl
.............\impact_impact.xwbt
.............\.seconfig\clk_gen.xreport
.............\.........\uart.xreport
.............\.........\uart_fpga4fun.projectmgr
.............\pa.fromHdl.tcl
.............\.lanAhead_run_1\planAhead.jou
.............\...............\planAhead.log
.............\...............\planAhead_run.log
.............\...............\uart_fpga4fun.data\constrs_1\designprops.xml
.............\...............\..................\.........\fileset.xml
.............\...............\..................\.........\usercols.xml
.............\...............\..................\sources_1\chipscope.xml
.............\...............\..................\.........\fileset.xml
.............\...............\..................\.........\ports.xml
.............\...............\..................\wt\webtalk_pa.xml
.............\...............\uart_fpga4fun.ppr
.............\uart.bgn
.............\uart.bit
.............\uart.bld
.............\uart.cmd_log
.............\uart.drc
.............\uart.ipf
.............\uart.lso
.............\uart.ncd
.............\uart.ngc
.............\uart.ngd
.............\uart.ngr
.............\uart.pad
.............\uart.par
.............\uart.pcf
.............\uart.prj
.............\uart.ptwx
.............\uart.stx
.............\uart.syr
.............\uart.twr
.............\uart.twx
.............\uart.ucf
.............\uart.unroutes
.............\uart.ut
.............\uart.v
.............\uart.xpi
.............\uart.xst
.............\uartrx.v
.............\uarttx.bmm
.............\uarttx.v
.............\uart_bitgen.xwbt
.............\uart_envsettings.html
.............\uart_fpga4fun.gise
.............\uart_fpga4fun.xise
.............\uart_guide.ncd
.............\uart_map.map
.............\uart_map.mrp
.............\uart_map.ncd
.............\uart_map.ngm
.............\uart_map.xrpt
.............\uart_ngdbuild.xrpt
.............\uart_pad.csv
.............\uart_pad.txt
.............\uart_par.xrpt
.............\uart_summary.html
.............\uart_summary.xml
.............\uart_usage.xml
.............\uart_xst.xrpt
.............\usage_statistics_webtalk.html
.............\webtalk.log
.............\webtalk_impact.xml
.............\webtalk_pn.xml
.............\xlnx_auto_0_xdb\cst.xbcd
.............\.st\work\hdllib.ref
.............\...\....\vlg32\async__transmitter.bin
.............\...\....\....A\async__receiver.bin
.............\...\....\...48\uart.bin
.............\_ngo\netlist.lst
.............\.xmsgs\bitgen.xmsgs
.............\......\map.xmsgs
.............\......\ngdbuild.xmsgs
.............\......\par.xmsgs
.............\......\pn_parser.xmsgs
.............\......\trce.xmsgs
.............\......\xst.xmsgs
.............\xst\dump.xst\uart.prj\ngx\notopt
.............\...\........\........\...\opt
.............\...\........\........\ngx
.............\planAhead_run_1\uart_fpga4fun.data\constrs_1
.............\...............\..................\sources_1
.............\...............\..................\wt
.............\xst\dump.xst\uart.prj
.............\...\work\vlg32
.............\...\....\vlg3A
.............\...\....\vlg48
.............\planAhead_run_1\uart_fpga4fun.data
.............\uart_xdb\tmp
.............\xst\dump.xst
.............\...\projnav.tmp
.............\...\work

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