library ieee use ieee.std_logic_1164.all use ieee.std_logic_arith.all use ieee.std_logic_unsigned.all entity ymq is port(num:in std_logic_vector(3 downto 0) dout:out std_logic_vector(0 TO 6)) end ymq architecture a1 of ymq is begin

28M分频器.txt
D触发器.txt
JK触发器.txt

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．