Introduction - If you have any usage issues, please Google them yourself
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY D74LS74 is
port(clk,clr,PRE,D:in std_logic
QT,QTN:out std_logic)
end ENTITY D74LS74
architecture bhv of D74LS74 is
signal q,qn:std_logic
signal x:std_logic
begin
x<=d