In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU and other modules

CPU
...\ACC.bsf
...\ACC.vhd
...\ACC.vhd.bak
...\ALU.bsf
...\ALU.vhd
...\ALU.vhd.bak
...\BR.bsf
...\BR.vhd
...\BR.vhd.bak
...\CPU.asm.rpt
...\CPU.bdf
...\CPU.done
...\CPU.fit.rpt
...\CPU.fit.smsg
...\CPU.fit.summary
...\CPU.flow.rpt
...\CPU.map.rpt
...\CPU.map.summary
...\CPU.pin
...\CPU.qpf
...\CPU.qsf
...\CPU.qws
...\CPU.sim.rpt
...\CPU.tan.rpt
...\CPU.tan.summary
...\CPU.vwf
...\CU.bsf
...\CU.vhd
...\CU.vhd.bak
...\db
...\..\altsyncram_3nd1.tdf
...\..\altsyncram_6pa1.tdf
...\..\altsyncram_6rf1.tdf
...\..\altsyncram_7gd1.tdf
...\..\altsyncram_8rc1.tdf
...\..\altsyncram_9o71.tdf
...\..\altsyncram_9qc1.tdf
...\..\altsyncram_b2g1.tdf
...\..\altsyncram_e1d1.tdf
...\..\altsyncram_e7d1.tdf
...\..\altsyncram_ik61.tdf
...\..\altsyncram_ir71.tdf
...\..\altsyncram_jed1.tdf
...\..\altsyncram_mrc1.tdf
...\..\altsyncram_qsc1.tdf
...\..\altsyncram_r8d1.tdf
...\..\altsyncram_rrc1.tdf
...\..\CPU.asm.qmsg
...\..\CPU.cbx.xml
...\..\CPU.cmp.bpm
...\..\CPU.cmp.cdb
...\..\CPU.cmp.ecobp
...\..\CPU.cmp.hdb
...\..\CPU.cmp.logdb
...\..\CPU.cmp.rdb
...\..\CPU.cmp.tdb
...\..\CPU.cmp0.ddb
...\..\CPU.cmp_bb.cdb
...\..\CPU.cmp_bb.hdb
...\..\CPU.cmp_bb.logdb
...\..\CPU.cmp_bb.rcf
...\..\CPU.dbp
...\..\CPU.db_info
...\..\CPU.eco.cdb
...\..\CPU.eds_overflow
...\..\CPU.fit.qmsg
...\..\CPU.fnsim.cdb
...\..\CPU.fnsim.hdb
...\..\CPU.fnsim.qmsg
...\..\CPU.hier_info
...\..\CPU.hif
...\..\CPU.map.bpm
...\..\CPU.map.cdb
...\..\CPU.map.ecobp
...\..\CPU.map.hdb
...\..\CPU.map.logdb
...\..\CPU.map.qmsg
...\..\CPU.map_bb.cdb
...\..\CPU.map_bb.hdb
...\..\CPU.map_bb.logdb
...\..\CPU.pre_map.cdb
...\..\CPU.pre_map.hdb
...\..\CPU.psp
...\..\CPU.pss
...\..\CPU.rtlv.hdb
...\..\CPU.rtlv_sg.cdb
...\..\CPU.rtlv_sg_swap.cdb
...\..\CPU.sgdiff.cdb
...\..\CPU.sgdiff.hdb
...\..\CPU.signalprobe.cdb
...\..\CPU.sim.cvwf
...\..\CPU.sim.hdb
...\..\CPU.sim.qmsg
...\..\CPU.sim.rdb
...\..\CPU.simfam
...\..\CPU.sim_ori.vwf
...\..\CPU.sld_design_entry.sci
...\..\CPU.sld_design_entry_dsc.sci
...\..\CPU.syn_hier_info

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．