This an AND gate 2 inputs and the output is the AND of the inputs.

and_gate\and_gate.asm.rpt
........\and_gate.bsf
........\and_gate.cdf
........\and_gate.done
........\and_gate.fit.rpt
........\and_gate.fit.summary
........\and_gate.flow.rpt
........\and_gate.jdi
........\and_gate.map.rpt
........\and_gate.map.summary
........\and_gate.pin
........\and_gate.qpf
........\and_gate.qsf
........\and_gate.sof
........\and_gate.sta.rpt
........\and_gate.sta.summary
........\and_gate.v
........\and_gate.v.bak
........\db\and_gate.amm.cdb
........\..\and_gate.asm.qmsg
........\..\and_gate.asm.rdb
........\..\and_gate.asm_labs.ddb
........\..\and_gate.cbx.xml
........\..\and_gate.cmp.bpm
........\..\and_gate.cmp.cdb
........\..\and_gate.cmp.hdb
........\..\and_gate.cmp.kpt
........\..\and_gate.cmp.logdb
........\..\and_gate.cmp.rdb
........\..\and_gate.cmp_merge.kpt
........\..\and_gate.db_info
........\..\and_gate.fit.qmsg
........\..\and_gate.hier_info
........\..\and_gate.hif
........\..\and_gate.idb.cdb
........\..\and_gate.lpc.html
........\..\and_gate.lpc.rdb
........\..\and_gate.lpc.txt
........\..\and_gate.map.bpm
........\..\and_gate.map.cdb
........\..\and_gate.map.hdb
........\..\and_gate.map.kpt
........\..\and_gate.map.logdb
........\..\and_gate.map.qmsg
........\..\and_gate.map_bb.cdb
........\..\and_gate.map_bb.hdb
........\..\and_gate.map_bb.logdb
........\..\and_gate.pre_map.cdb
........\..\and_gate.pre_map.hdb
........\..\and_gate.root_partition.map.reg_db.cdb
........\..\and_gate.rpp.qmsg
........\..\and_gate.rtlv.hdb
........\..\and_gate.rtlv_sg.cdb
........\..\and_gate.rtlv_sg_swap.cdb
........\..\and_gate.sgate.rvd
........\..\and_gate.sgate_sm.rvd
........\..\and_gate.sgdiff.cdb
........\..\and_gate.sgdiff.hdb
........\..\and_gate.sld_design_entry.sci
........\..\and_gate.sld_design_entry_dsc.sci
........\..\and_gate.smart_action.txt
........\..\and_gate.sta.qmsg
........\..\and_gate.sta.rdb
........\..\and_gate.sta_cmp.7_slow_1200mv_85c.tdb
........\..\and_gate.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\and_gate.stingray_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
........\..\and_gate.stingray_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
........\..\and_gate.syn_hier_info
........\..\and_gate.tiscmp.fast_1200mv_0c.ddb
........\..\and_gate.tiscmp.slow_1200mv_0c.ddb
........\..\and_gate.tiscmp.slow_1200mv_85c.ddb
........\..\and_gate.tis_db_list.ddb
........\..\and_gate.tmw_info
........\..\logic_util_heursitic.dat
........\..\prev_cmp_and_gate.qmsg
........\incremental_db\compiled_partitions\and_gate.db_info
........\..............\...................\and_gate.root_partition.cmp.cdb
........\..............\...................\and_gate.root_partition.cmp.dfp
........\..............\...................\and_gate.root_partition.cmp.hdb
........\..............\...................\and_gate.root_partition.cmp.kpt
........\..............\...................\and_gate.root_partition.cmp.logdb
........\..............\...................\and_gate.root_partition.cmp.rcfdb
........\..............\...................\and_gate.root_partition.map.cdb
........\..............\...................\and_gate.root_partition.map.dpi
........\..............\...................\and_gate.root_partition.map.hbdb.cdb
........\..............\...................\and_gate.root_partition.map.hbdb.hb_info
........\..............\...................\and_gate.root_partition.map.hbdb.hdb
........\..............\...................\and_gate.root_partition.map.hbdb.sig
........\..............\...................\and_gate.root_partition.map.hdb
........\..............\...................\and_gate.root_partition.map.kpt
........\..............\README
........\..............\compiled_partitions
........\db
........\incremental_db
and_gate

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