Introduction - If you have any usage issues, please Google them yourself
Frequency selection system. the inclk0 side input 25MHz signal, multiplier by altpll at 400MHz signal C0-ended output, demand not the same as their own to change the parameters of frequency multiplier. The divider clkdiv used divided by two, divide-eighth of the frequency, and 16 divided by, respectively, are at a frequency of 200MHz, 100MHz, 50MHz, 25MHz four kinds of frequency signals input to the selector. Select the TCLK is an external input signal, A [3 .. 0] four separate buttons, selector all the way to the output with a different combination of buttons to choose from the four sub-frequency preferences and TCLK. Code is clear and easy to understand, does not meet the needs of your own expansion