NETFPGA reference route and reference switches in the code, a detailed description of the implementation process of the switch.

switch\add_hdr.v
......\add_rm_hdr.v
......\arbitrator.v
......\cnet_sram_sm.v
......\cpu_dma_queue.v
......\cpu_dma_queue_no_regs.v
......\cpu_dma_queue_regs.v
......\cpu_dma_rx_queue.v
......\cpu_dma_tx_queue.v
......\decoder.v
......\device_id_reg.v
......\dump.v
......\ethernet_parser.v
......\ethernet_parser_32bit.v
......\ethernet_parser_64bit.v
......\fallthrough_small_fifo.v
......\fallthrough_small_fifo_v2.v
......\gene_ankur.ppt
......\gig_eth_mac.v
......\input_arbiter.v
......\in_arb_regs.v
......\lfsr32.v
......\mac_cam_lut.v
......\NetFPGA_Dev_2010_Scaling_the_NetFPGA_switch_using_Aurora_over_SATA.pdf
......\nf2_core.v
......\nf2_dma.v
......\nf2_dma_bus_fsm.v
......\nf2_dma_que_intfc.v
......\nf2_dma_regs.v
......\nf2_dma_sync.v
......\nf2_mdio.v
......\nf2_reg_grp.v
......\nf2_top.v
......\NF_All_defines.v
......\op_lut_regs.v
......\oq_header_parser.v
......\oq_regs.v
......\oq_regs_ctrl.v
......\oq_regs_dual_port_ram.v
......\oq_regs_eval_empty.v
......\oq_regs_eval_full.v
......\oq_regs_generic_reg_grp.v
......\oq_regs_host_iface.v
......\oq_reg_helper.v
......\oq_reg_instances.v
......\output_port_lookup.v
......\output_queues.v
......\priority_encoder.v
......\pulse_synchronizer.v
......\reg_grp.v
......\remove_pkt.v
......\rgmii_io.v
......\rm_hdr.v
......\rotate.v
......\small_async_fifo.v
......\small_fifo.v
......\small_fifo_v2.v
......\small_fifo_v3.v
......\sram_arbiter.v
......\sram_reg_access.v
......\store_pkt.v
......\udp_reg_master.v
......\unused_reg.v
......\user_data_path.v
switch

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