Introduction - If you have any usage issues, please Google them yourself
This paper designed a 16 signed/unsigned binary number multiplication of the multiplier can be achieved. The multiplier complement a multiply (Booth algorithm), simplifying the number of partial product, reducing some of the addition operation, thereby improving the operation speed. The multiplier Verilog code through Modelsim software on the corresponding waveform simulation, source code compile comprehensive and through QuartusII software.