Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language

Packet : 9927394sine.rar filelist
sine\default.cfg
sine\default.cfg.bck
sine\ROM.DAT
sine\rom16x7.v
sine\sgen.c
sine\sim.vc
sine\simv.exe
sine\simv.exp
sine\simv.lib
sine\sine.v
sine\sinetest.v
sine\vcdplus.vpd
sine\wave.bat
sine\simv.daidir\01j9_1.daidb
sine\simv.daidir\3e3i_1.daidb
sine\simv.daidir\vcs.dailu
sine\simv.daidir\vcs_mstr.daidb
sine\simv.daidir
sine

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