Introduction - If you have any usage issues, please Google them yourself
This is a FPGA-BCD Encoder design. Compilers can be downloaded to the device simulation Altea.
Packet : 101259355bcdencode.rar filelist
example_proj\cmp_state.ini
example_proj\db\altsyncram_njc1.tdf
example_proj\db\example_proj.db_info
example_proj\db\example_proj.project.hdb
example_proj\db\example_proj.proj_top.sld_design_entry.sci
example_proj\db\proj_top(0).cnf.cdb
example_proj\db\proj_top(0).cnf.hdb
example_proj\db\proj_top(1).cnf.cdb
example_proj\db\proj_top(1).cnf.hdb
example_proj\db\proj_top(2).cnf.cdb
example_proj\db\proj_top(2).cnf.hdb
example_proj\db\proj_top.asm.qmsg
example_proj\db\proj_top.cmp.cdb
example_proj\db\proj_top.cmp.ddb
example_proj\db\proj_top.cmp.hdb
example_proj\db\proj_top.cmp.rdb
example_proj\db\proj_top.cmp.tdb
example_proj\db\proj_top.csf.qmsg
example_proj\db\proj_top.fit.qmsg
example_proj\db\proj_top.hif
example_proj\db\proj_top.map.cdb
example_proj\db\proj_top.map.hdb
example_proj\db\proj_top.map.qmsg
example_proj\db\proj_top.pre_map.hdb
example_proj\db\proj_top.rtlv.hdb
example_proj\db\proj_top.rtlv_sg.cdb
example_proj\db\proj_top.rtlv_sg_swap.cdb
example_proj\db\proj_top.sgdiff.cdb
example_proj\db\proj_top.sgdiff.hdb
example_proj\db\proj_top.tan.qmsg
example_proj\db\proj_top_cmp.qrpt
example_proj\db\proj_top_hier_info
example_proj\db\proj_top_syn_hier_info
example_proj\example_proj.qpf
example_proj\example_proj.qws
example_proj\proj_top.qsf
example_proj\proj_top.v
example_proj\proj_top_bb.v
example_proj\RAMs.mif
example_proj\db
example_proj