only for verilog , this is single cycle code for verilog

lab3\COLAB Project Assignment 3_PPT.pdf
....\Computer Organization Project3-chinese.pdf
....\Computer Organization Project3_english.pdf
....\source code\ALU.v
....\...........\answer1.txt
....\...........\answer2.txt
....\...........\CPU.v
....\...........\DM.v
....\...........\IDecoder.v
....\...........\IM.v
....\...........\Mux_ALU_Src.v
....\...........\Mux_MemToReg.v
....\...........\Mux_PC_Src1.v
....\...........\Mux_PC_Src2.v
....\...........\Mux_Reg_Dst.v
....\...........\PC.v
....\...........\Reg.v
....\...........\Sign_Extend.v
....\...........\test1.txt
....\...........\test2.txt
....\...........\TestBench.v
....\source code
lab3

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