Introduction - If you have any usage issues, please Google them yourself
I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
Packet : 79419115testbench.rar filelist
testbench\ADPLL.cr.mti
testbench\adpll.mpf
testbench\ADPLL.v
testbench\ADPLL.v.bak
testbench\tb_adpll.acf
testbench\tb_adpll.hif
testbench\tb_ADPLL.v
testbench\tb_ADPLL.v.bak
testbench\vsim.wlf
testbench\work\@a@d@p@l@l\verilog.asm
testbench\work\@a@d@p@l@l\_primary.dat
testbench\work\@a@d@p@l@l\_primary.vhd
testbench\work\@a@d@p@l@l
testbench\work\tb_@a@d@p@l@l\verilog.asm
testbench\work\tb_@a@d@p@l@l\_primary.dat
testbench\work\tb_@a@d@p@l@l\_primary.vhd
testbench\work\tb_@a@d@p@l@l
testbench\work\_info
testbench\work
testbench