The FPGA simulation realization of traffic light control system, language, Verilog, environment QurtursII, default preset time countdown, support manual control mode for a direction signal lamps lit. Signal lights using LED instead

Traffic_Light\contral.v
.............\contral.v.bak
.............\db\logic_util_heursitic.dat
.............\..\prev_cmp_traffic_light.qmsg
.............\..\traffic_light.amm.cdb
.............\..\traffic_light.asm.qmsg
.............\..\traffic_light.asm.rdb
.............\..\traffic_light.cbx.xml
.............\..\traffic_light.cmp.bpm
.............\..\traffic_light.cmp.cbp
.............\..\traffic_light.cmp.cdb
.............\..\traffic_light.cmp.hdb
.............\..\traffic_light.cmp.kpt
.............\..\traffic_light.cmp.logdb
.............\..\traffic_light.cmp.rdb
.............\..\traffic_light.cmp0.ddb
.............\..\traffic_light.cmp_merge.kpt
.............\..\traffic_light.db_info
.............\..\traffic_light.eda.qmsg
.............\..\traffic_light.fit.qmsg
.............\..\traffic_light.hier_info
.............\..\traffic_light.hif
.............\..\traffic_light.idb.cdb
.............\..\traffic_light.lpc.html
.............\..\traffic_light.lpc.rdb
.............\..\traffic_light.lpc.txt
.............\..\traffic_light.map.bpm
.............\..\traffic_light.map.cbp
.............\..\traffic_light.map.cdb
.............\..\traffic_light.map.hdb
.............\..\traffic_light.map.kpt
.............\..\traffic_light.map.logdb
.............\..\traffic_light.map.qmsg
.............\..\traffic_light.map_bb.cdb
.............\..\traffic_light.map_bb.hdb
.............\..\traffic_light.map_bb.logdb
.............\..\traffic_light.pre_map.cdb
.............\..\traffic_light.pre_map.hdb
.............\..\traffic_light.rpp.qmsg
.............\..\traffic_light.rtlv.hdb
.............\..\traffic_light.rtlv_sg.cdb
.............\..\traffic_light.rtlv_sg_swap.cdb
.............\..\traffic_light.sgate.rvd
.............\..\traffic_light.sgate_sm.rvd
.............\..\traffic_light.sgdiff.cdb
.............\..\traffic_light.sgdiff.hdb
.............\..\traffic_light.sld_design_entry.sci
.............\..\traffic_light.sld_design_entry_dsc.sci
.............\..\traffic_light.smart_action.txt
.............\..\traffic_light.smp_dump.txt
.............\..\traffic_light.sta.qmsg
.............\..\traffic_light.sta.rdb
.............\..\traffic_light.sta_cmp.8_slow.tdb
.............\..\traffic_light.syn_hier_info
.............\..\traffic_light.tan.qmsg
.............\..\traffic_light.tis_db_list.ddb
.............\..\traffic_light.tmw_info
.............\display.v
.............\display.v.bak
.............\disp_573.v
.............\disp_573.v.bak
.............\fre_div.v
.............\incremental_db\compiled_partitions\traffic_light.db_info
.............\..............\...................\traffic_light.root_partition.cmp.cdb
.............\..............\...................\traffic_light.root_partition.cmp.dfp
.............\..............\...................\traffic_light.root_partition.cmp.hdb
.............\..............\...................\traffic_light.root_partition.cmp.kpt
.............\..............\...................\traffic_light.root_partition.cmp.logdb
.............\..............\...................\traffic_light.root_partition.cmp.rcfdb
.............\..............\...................\traffic_light.root_partition.cmp.re.rcfdb
.............\..............\...................\traffic_light.root_partition.map.cdb
.............\..............\...................\traffic_light.root_partition.map.dpi
.............\..............\...................\traffic_light.root_partition.map.hdb
.............\..............\...................\traffic_light.root_partition.map.kpt
.............\..............\README
.............\simulation\modelsim\modelsim.ini
.............\..........\........\msim_transcript
.............\..........\........\rtl_work\contral\verilog.prw
.............\..........\........\........\.......\verilog.psm
.............\..........\........\........\.......\_primary.dat
.............\..........\........\........\.......\_primary.dbs
.............\..........\........\........\.......\_primary.vhd
.............\..........\........\........\disp_573\verilog.prw
.............\..........\........\........\........\verilog.psm
.............\....

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