1. RISC work every eight clock cycles to execute an instruction needs. RISC reset and start by rst control, rst active high. Rst is low, the first CPUs fetch arrives starting from Rom s 000 start reading instruction, the first three cycles for reading instruction. When the read operation is performed on the bus, at 3.5 cycles, memory, or port address output to the address bus, 4- 6 clock cycles, and the read signal rd, read data to the bus, a logic operation. 7 clock cycles, rd invalid, 7.5 PC clock address output address, ready for the next instruction The write operation on the bus, in Section 3.5 of the clock cycle, to establish a write address, and four clock cycles and output data, the fifth clock cycle output write signal. To the end of the six clock the 7.5 clock address output PC address, ready for the next instruction cycle. Operation: new construction, the compiler compile all, and simulation, join in the wave window to observe the signal, then the run-all completed by the

RISC_CPU
........\accum.v
........\accum.v.bak
........\addr_decode.v
........\adr.v
........\alu.v
........\clk_gen.v
........\counter.v
........\cpu.cr.mti
........\cpu.mpf
........\cpu.v
........\cputop.v
........\datactl.v
........\machine.v
........\machinectl.v
........\ram.v
........\register.v
........\RISC_CPU报告_修改_田连泉.docx
........\rom.v
........\test1.dat
........\test1.JPG
........\test1.pro
........\test1_w.JPG
........\test2.dat
........\test2.JPG
........\test2.pro
........\test2_w.JPG
........\test3.dat
........\test3.JPG
........\test3.pro
........\test3_w.JPG
........\transcript
........\vsim.wlf
........\work
........\....\accum
........\....\.....\verilog.prw
........\....\.....\verilog.psm
........\....\.....\_primary.dat
........\....\.....\_primary.dbs
........\....\.....\_primary.vhd
........\....\addr_decode
........\....\...........\verilog.prw
........\....\...........\verilog.psm
........\....\...........\_primary.dat
........\....\...........\_primary.dbs
........\....\...........\_primary.vhd
........\....\adr
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\alu
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\clk_gen
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\counter
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\cpu
........\....\cputop
........\....\......\verilog.prw
........\....\......\verilog.psm
........\....\......\_primary.dat
........\....\......\_primary.dbs
........\....\......\_primary.vhd
........\....\...\verilog.prw
........\....\...\verilog.psm
........\....\...\_primary.dat
........\....\...\_primary.dbs
........\....\...\_primary.vhd
........\....\datactl
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd
........\....\machine
........\....\machinectl
........\....\..........\verilog.prw
........\....\..........\verilog.psm
........\....\..........\_primary.dat
........\....\..........\_primary.dbs
........\....\..........\_primary.vhd
........\....\.......\verilog.prw
........\....\.......\verilog.psm
........\....\.......\_primary.dat
........\....\.......\_primary.dbs
........\....\.......\_primary.vhd

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