This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.

aasd.v
alu.v
clk_gen.v
control.v
counter.v
cpu.v
initmem.dat
mem32by8.v
register.v
scale_mux.v
tb_cpu.v

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