Mips architecture cpu with verilog description c language mips assembly language to write a program, translated into machine code can then cpu running on. Simulation results exactly three.

Csrc
....\C.CPP
....\C.DSP
....\C.DSW
....\C.ncb
....\C.OPT
....\C.PLG
....\Debug
....\.....\C.exe
....\.....\C.ilk
....\.....\C.obj
....\.....\C.pch
....\.....\C.pdb
....\.....\vc60.idb
....\.....\vc60.pdb
Msrc
....\code.s
project
.......\Add_tb.jpg
.......\ALUControl_tb.jpg
.......\ALU_tb.jpg
.......\Control_tb.jpg
.......\Counter_tb.jpg
.......\DataMemory_tb.jpg
.......\InsMemory_tb.jpg
.......\Mux_tb.jpg
.......\PC_tb.jpg
.......\project.pdf
.......\project.wps
.......\Registers_tb.jpg
.......\ShiftLeft2_tb.jpg
.......\SignExtend_tb.jpg
reference
.........\0_2 常用模块的Verilog HDL设计.pdf
.........\chart.jpg
.........\chart.psd
.........\MIPS ISA.pdf
.........\MIPS Reference Card.pdf
.........\SPIM.pdf
.........\True Value.xls
.........\Verilog HDL硬件描述语言（入门级）.pdf
.........\verilog_内存建模.pdf
.........\Verilog代码书写规范.pdf
.........\数字系统设计2_2012Project1.doc
.........\数字系统设计2_2012Project1.pdf
sim
...\Add_test.cr.mti
...\Add_test.mpf
...\ALUCountrol_test.cr.mti
...\ALUCountrol_test.mpf
...\ALU_test.cr.mti
...\ALU_test.mpf
...\Control_test.cr.mti
...\Control_test.mpf
...\Counter_test.cr.mti
...\Counter_test.mpf
...\CPU.cr.mti
...\CPU.mpf
...\DataMemory.txt
...\DataMemory_test.cr.mti
...\DataMemory_test.mpf
...\InsMemory.txt
...\InsMemory_test.cr.mti
...\InsMemory_test.mpf
...\Mux_test.cr.mti
...\Mux_test.mpf
...\PC_test.cr.mti
...\PC_test.mpf
...\Registers.txt
...\Registers_test.cr.mti
...\Registers_test.mpf
...\ShiftLeft2_test.cr.mti
...\ShiftLeft2_test.mpf
...\SignExtend_test.cr.mti
...\SignExtend_test.mpf
...\transcript
...\vsim.wlf
...\vsim_stacktrace.vstf
...\work
...\....\@a@l@u
...\....\@a@l@u@control
...\....\..............\_primary.dat
...\....\..............\_primary.dbs
...\....\..............\_primary.vhd
...\....\@a@l@u@control_tb
...\....\.................\_primary.dat
...\....\.................\_primary.dbs
...\....\.................\_primary.vhd
...\....\......\_primary.dat
...\....\......\_primary.dbs
...\....\......\_primary.vhd
...\....\@a@l@u_tb
...\....\.........\_primary.dat
...\....\.........\_primary.dbs
...\....\.........\_primary.vhd
...\....\@add
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\@add_tb

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