Verilog realization shiftreg, with the test document. Document rather complete, and can be downloaded to test the

Packet : 19854799shiftreg.rar filelist
shiftreg\cmp_state.ini
shiftreg\db\shiftreg(0).cnf.cdb
shiftreg\db\shiftreg(0).cnf.hdb
shiftreg\db\shiftreg(1).cnf.cdb
shiftreg\db\shiftreg(1).cnf.hdb
shiftreg\db\shiftreg-sim.vwf
shiftreg\db\shiftreg.asm.qmsg
shiftreg\db\shiftreg.cmp.cdb
shiftreg\db\shiftreg.cmp.ddb
shiftreg\db\shiftreg.cmp.hdb
shiftreg\db\shiftreg.cmp.rdb
shiftreg\db\shiftreg.cmp.tdb
shiftreg\db\shiftreg.csf.qmsg
shiftreg\db\shiftreg.db_info
shiftreg\db\shiftreg.fit.qmsg
shiftreg\db\shiftreg.hif
shiftreg\db\shiftreg.map.cdb
shiftreg\db\shiftreg.map.hdb
shiftreg\db\shiftreg.map.qmsg
shiftreg\db\shiftreg.pre_map.hdb
shiftreg\db\shiftreg.project.hdb
shiftreg\db\shiftreg.rtlv.hdb
shiftreg\db\shiftreg.rtlv_sg.cdb
shiftreg\db\shiftreg.rtlv_sg_swap.cdb
shiftreg\db\shiftreg.sgdiff.cdb
shiftreg\db\shiftreg.sgdiff.hdb
shiftreg\db\shiftreg.shiftreg.sld_design_entry.sci
shiftreg\db\shiftreg.sim.hdb
shiftreg\db\shiftreg.sim.qmsg
shiftreg\db\shiftreg.sim.rdb
shiftreg\db\shiftreg.tan.qmsg
shiftreg\db\shiftreg_cmp.qrpt
shiftreg\db\shiftreg_hier_info
shiftreg\db\shiftreg_sim.qrpt
shiftreg\db\shiftreg_syn_hier_info
shiftreg\shiftreg.asm.rpt
shiftreg\shiftreg.bdf
shiftreg\shiftreg.done
shiftreg\shiftreg.fit.eqn
shiftreg\shiftreg.fit.rpt
shiftreg\shiftreg.flow.rpt
shiftreg\shiftreg.map.eqn
shiftreg\shiftreg.map.rpt
shiftreg\shiftreg.pin
shiftreg\shiftreg.pof
shiftreg\shiftreg.qpf
shiftreg\shiftreg.qsf
shiftreg\shiftreg.qws
shiftreg\shiftreg.sim.rpt
shiftreg\shiftreg.sof
shiftreg\shiftreg.tan.rpt
shiftreg\shiftreg.tan.summary
shiftreg\shiftreg.v
shiftreg\shiftreg.vhd
shiftreg\shiftreg.vwf
shiftreg\shiftreg_1.v
shiftreg\shiftreg_1.vhd
shiftreg\shiftreg_2.v
shiftreg\shiftreg_2.vhd
shiftreg\shiftreg_3.v
shiftreg\shiftreg_3.vhd
shiftreg\shiftreg_4.v
shiftreg\shiftreg_4.vhd
shiftreg\shiftreg_5.vhd
shiftreg\shiftreg_7.vhd
shiftreg\shiftreg_8.vhd
shiftreg\shiftreg_assignment_defaults.qdf
shiftreg\sim.cfg
shiftreg\db\穝戈

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