SDRAM IP CORE,ALTERA

sdr-sdram-verilog\readme_sdr_sdram.txt
.................\sdr_sdram.pdf
.................\.imulation\sdr_sdram_tb.v
.................\..........\sdr_sdram_tb.v.bak
.................\.ource\altclklock.v
.................\......\Command.v
.................\......\Command.v.bak
.................\......\compile_all.v
.................\......\control_interface.v
.................\......\Params.v
.................\......\Params.v.bak
.................\......\PLL1.v
.................\......\sdr_data_path.v
.................\......\sdr_sdram.v
.................\doc
.................\simulation
.................\source
sdr-sdram-verilog

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