5 stage DLX pipeline implemented in verilog

12060006 陈祥 体系结构第五次实验（DLX流水线）\12060006 陈祥 DLX流水线.docx
.............................................\~$060006 陈祥 DLX流水线.docx
.............................................\截图\ise工程.png
.............................................\....\仿真.png
.............................................\....\网表.png
.............................................\所有src\controller.v
.............................................\.......\dlx.v
.............................................\.......\dlx_pipeline.v
.............................................\.......\EX_stage.v
.............................................\.......\ID_stage.v
.............................................\.......\IF_stage.v
.............................................\.......\memory.v
.............................................\.......\MEM_stage.v
.............................................\.......\mem_wrapper.v
.............................................\.......\opcode.v
.............................................\.......\regfiles.v
.............................................\.......\WB_stage.v
.............................................\测试程序src\dlx_tb.v
.............................................\...........\memfile.dat
.............................................\截图
.............................................\所有src
.............................................\测试程序src
12060006 陈祥 体系结构第五次实验（DLX流水线）

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