A VGA display program

vga
...\vga_test
...\........\db
...\........\..\logic_util_heursitic.dat
...\........\..\prev_cmp_vga_test.qmsg
...\........\..\vga_test.amm.cdb
...\........\..\vga_test.asm.qmsg
...\........\..\vga_test.asm.rdb
...\........\..\vga_test.asm_labs.ddb
...\........\..\vga_test.cbx.xml
...\........\..\vga_test.cmp.bpm
...\........\..\vga_test.cmp.cdb
...\........\..\vga_test.cmp.hdb
...\........\..\vga_test.cmp.kpt
...\........\..\vga_test.cmp.logdb
...\........\..\vga_test.cmp.rdb
...\........\..\vga_test.cmp0.ddb
...\........\..\vga_test.cmp1.ddb
...\........\..\vga_test.cmp2.ddb
...\........\..\vga_test.cmp_merge.kpt
...\........\..\vga_test.db_info
...\........\..\vga_test.eda.qmsg
...\........\..\vga_test.fit.qmsg
...\........\..\vga_test.hier_info
...\........\..\vga_test.hif
...\........\..\vga_test.idb.cdb
...\........\..\vga_test.lpc.html
...\........\..\vga_test.lpc.rdb
...\........\..\vga_test.lpc.txt
...\........\..\vga_test.map.bpm
...\........\..\vga_test.map.cdb
...\........\..\vga_test.map.hdb
...\........\..\vga_test.map.kpt
...\........\..\vga_test.map.logdb
...\........\..\vga_test.map.qmsg
...\........\..\vga_test.map.rdb
...\........\..\vga_test.map_bb.cdb
...\........\..\vga_test.map_bb.hdb
...\........\..\vga_test.map_bb.logdb
...\........\..\vga_test.pre_map.cdb
...\........\..\vga_test.pre_map.hdb
...\........\..\vga_test.root_partition.map.reg_db.cdb
...\........\..\vga_test.routing.rdb
...\........\..\vga_test.rtlv.hdb
...\........\..\vga_test.rtlv_sg.cdb
...\........\..\vga_test.rtlv_sg_swap.cdb
...\........\..\vga_test.sgdiff.cdb
...\........\..\vga_test.sgdiff.hdb
...\........\..\vga_test.sld_design_entry.sci
...\........\..\vga_test.sld_design_entry_dsc.sci
...\........\..\vga_test.smart_action.txt
...\........\..\vga_test.sta.qmsg
...\........\..\vga_test.sta.rdb
...\........\..\vga_test.sta_cmp.8_slow.tdb
...\........\..\vga_test.syn_hier_info
...\........\..\vga_test.tis_db_list.ddb
...\........\..\vga_test.tmw_info
...\........\incremental_db
...\........\..............\compiled_partitions
...\........\..............\...................\vga_test.db_info
...\........\..............\...................\vga_test.root_partition.cmp.cdb
...\........\..............\...................\vga_test.root_partition.cmp.dfp
...\........\..............\...................\vga_test.root_partition.cmp.hdb
...\........\..............\...................\vga_test.root_partition.cmp.kpt
...\........\..............\...................\vga_test.root_partition.cmp.logdb
...\........\..............\...................\vga_test.root_partition.cmp.rcfdb
...\........\..............\...................\vga_test.root_partition.map.cdb
...\........\..............\...................\vga_test.root_partition.map.dpi
...\........\..............\...................\vga_test.root_partition.map.hbdb.cdb
...\........\..............\...................\vga_test.root_partition.map.hbdb.hb_info
...\........\..............\...................\vga_test.root_partition.map.hbdb.hdb
...\........\..............\...................\vga_test.root_partition.map.hbdb.sig
...\........\..............\...................\vga_test.root_partition.map.hdb
...\........\..............\...................\vga_test.root_partition.map.kpt
...\........\..............\README
...\........\simulation
...\........\..........\modelsim
...\........\..........\........\modelsim.ini
...\........\..........\........\msim_transcript
...\........\..........\........\rtl_work
...\........\..........\........\........\vga_test
...\........\..........\........\........\........\verilog.prw
...\........\..........\........\........\........\verilog.psm
...\........\..........\........\........\........\_primary.dat
...\........\..........\........\........\........\_primary.dbs
...\........\..........\........\........\........\_primary.vhd
...\........\..........\........\........\_info
...\........\..........\........\........\_temp
...\........\..........\........\........\_vmake
...\........\..........\........\vga_test.sft
...\........\..........\........\

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